Difference between revisions of "TF EIM Chapt6"

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Field Effect Transistors (FET, JFET, MOSFET)
  
==Load Line==
+
=Properties=
  
 +
FETs differ from the bipolar transistors in the las chapter in that the current from a FET is only due to the majority charge carriers in the semiconductor while bi-polar transistors current is produced from both carrier types; electron and hole.
  
The load line represents the bias conditions in which the <math>I_C -vs V_{CE}</math> dependence is linear;(i.e.: a constance Resistance).  Setting up a circuit which changes the transistor bias along the load line means that the transistor is behaving like a resistor.
+
*higher input impedance than bi-polar
 +
*less gain than bi-polar
 +
*better temperature stability
  
 +
=JFET =
  
Consider the collector-Emitter side of the transistor below.
+
JFET <math>\equiv</math>  Junction Field Effect Transistor
  
[[File:TF_EIM_LoadLineCircuit1.gif | 500 px]]
 
  
 +
In a bi-polar transistor you have a depletion region with mixed charge carriers
  
Kirchoff's loops theorem is
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{| border="3"  cellpadding="20" cellspacing="0"
 +
|[[File:TF_EIM_BipolarJunction.png| 200 px]] ||  [[File:TF_EIM_BipolarJunctionDiodeRep.png| 200 px]] ||[[File:TF_EIM_BipolarJunctionCircuit.png| 200 px]]
 +
|-
 +
| pnp bi-polar transistor || Equivalence circuit || Circuit diagram
 +
|-
 +
|}
  
<math>V_{CC} - I_CR_C -V_{CE} = 0</math>
 
  
<math>\Rightarrow</math>
+
In the Junction Field Effect Transistor you have a single charge carrier with the minority charge carriers forming a choke point for the majority carrier current flow.  It is similar to "pinching" a garden hose when water is flowing through it.
  
<math>I_C = \frac{V_{CC}}{R_C} - \frac{1}{R_C} V_{CE}</math>
 
  
A graph of <math>I_C -vs- V_{CE}</math> is a line with a slope of<math> - \frac{1}{R_C}</math> and a y-intercept of  <math>\frac{V_{CC}}{R_C}</math>.
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{| border="3"  cellpadding="20" cellspacing="0"
 +
|[[File:TF_EIM_JFETnchan.gif| 200 px]] ||  [[File:TF_EIM_nchanDiodeRep.jpg| 200 px]] ||[[File:TF_EIM_JFETnchanCircuit.jpeg| 200 px]]
 +
|-
 +
| JFET || Equivalence circuit || Circuit diagram
 +
|-
 +
|}
  
If <math>I_C=0</math> then <math>V_{CE} = V_{CC}</math>.
+
The semiconductor material of the gate is the opposite of the channel. Here the n-p (or p-n) junction is between the gate and the channel. 
  
The point Q_0 in the above curve represents a "Quiescent" (quiet) point where the best amplification occurs because it is in the middle of the operating pointIf you are designing an AC amplifier you will want to be at this point to have a wide amplifier range.  
+
The JFET operates by reverse biasing the gate-channel junction (diode) so the gate current doesn't flow in the direction indicated by the circuit diagram symbol.  This means that the current through the gate is small (nAmps)As a result the input impedance looking into the gate is high (M<math>\Omega</math>) for the equivalent circuit.
  
If you want to use the transistor for an analog signal (microphone-speaker) then you will want to operate the circuit near Q_0 and have a shallow load line.
+
The current junction rule is
  
Q_0 is the cutoff point where there is no output:ie; the base current is zero; the transistor has infinite resistance
+
:<math>I_D = I_S + I_G \approx I_S</math>
  
Q_S is the point where the amplifier is saturating.  The transistor is supplying its max current a signal going beyond will essentially be clipped.  The transistor has an effective resistance of zero at this point.
+
for the Bi-Polar transistor
  
 +
:<math>I_C=I_E +I_B \approx I_E</math>
  
 +
==Resistance==
  
If you want to make a digital switch then you want the load line as steep as possible so the circuit changes from Q_0 (off) to Q_S(on)  as fast as possible.
+
The FET acts like a resistor.
  
==Temperature Dependence==
+
Consider the following circuit
  
The voltage drop <math>V_{BC}</math> is a reverse voltage drop for the majority charge carriers BUT a forward voltage for the minority carriers. 
+
Let
  
As the temperature increases the impurity atoms tend to diffuse through the semiconductor from high concentration regions to low concentration regions. 
+
<math>V_{DD} =</math> the drain driving voltage
  
 +
<math>R_D</math> = resistor between the drain and V_{DD}
  
This means that for a pnp transistor, the thermally created electrons in the n-type base semiconductor will move towards the p-type emitter by crossing the base-emitter junction due to the forward voltage.
+
if
 +
<math>\rho</math> = resistivity of the n-type semiconductor
  
Similarly thermally excited holes in the p-type collector will flow to the p-type emitter due to the reverse voltage drop.
+
then
  
;<math>I_{CBO}</math>
+
:r = <math>\rho \frac{\ell}{A}</math> = resistance of the JFET
: The reverse current from the Collector to the Base with the emitter Open
 
  
The total current becomes
+
:<math>I_D = \frac{V_{DD}}{r+R_D}</math>
  
:<math>I_C = \alpha I_E + I_{CBO}</math>
+
If you reverse bias the gate then the depletion region at the p-n junction expands into the n-type material thereby reducing the cross-sectional area (A) of the channel.
  
The collector current increases and as a result the transistor temperature increases
+
==FET pinchoff==
  
The base current becomes
+
If you continue to reverse bias the gate, keeping V_{DD} constant, then the drain current will decrease as you make the gate more negative.
  
:<math>I_B = (1-\alpha)I_E - I_{CBO}</math>
+
The pinchoff condition will occur when the reverse bias is large enough to stop the drain current I_D.
  
So the base current becomes less but it is usually kept constant by the power source.
+
:<math>V_{GS(off)} = \mbox{pinchoff bias} = \frac{enT}{8 \epsilon}</math>
  
You have "thermal runaway" and the transistor may burn out.
+
where
  
To compensate for this increase you add a resistor to the emitter which hold <math>V_{EB}</math> constant.
+
:<math>\epsilon</math> = dielectric constant
 +
:<math>T</math> = thickness of the channel
 +
:<math>n</math> = number of impurity atoms per volume
  
  
[[File:TF_EIM_LoadLineTempControlledCircuit.png| 200 px]]
+
You can find the "pinchoff" voltage by making V_{GS} more negative (n-channel) until the drain current I_D becomes zero.
  
  
As<math> I_{CBO}</math> increases with temperature, the base voltage <math>V_B</math> becomes more positive (the increase <math>I_{CBO}</math> increases <math>V_{BE}</math> and thus you need less <math>V_B</math> to overcome the the base-emitter junction).
+
In the other extreme
  
:<math>V_{BE} = V_B - V_E</math>
+
:<math>I_{DSS} \equiv</math> Maximum drain current (current flows from Drain to Source with the gate Shorted; ie <math>V_{GS}</math> = 0)
  
As <math>V_B</math> goes more positive, <math>I_C</math> and <math> I_E</math> increase.  But since <math>V_E = I_E R_E</math>, <math>V_E</math> will increase.
+
==Temperature==
  
=Bipolar Transistor Amplifier=
+
Because of the way a JFET operates, by pinching the current, the device heats up less at higher currents because you are no longer restricting the current flow.
  
A npn bipolar transistor amplifier configured with a common emitter is shown below.
+
At low values of<math> I_D</math> and increase in the device temperature will cause an increase in <math>I_D</math>.
  
[[File:TF_EIM_Lab14a.png]]
+
But at high values of <math>I_D</math> the increase in temperature decreases <math>I_D</math>.
  
 +
This feature of the JFET allows you to chain several together for amplification such that if one starts to overheat it will amplify less.
  
Let's build this circuit starting with the above load line circuit that has been stabilized for temperature.
+
== Characteristic curve==
  
[[File:TF_EIM_LoadLineTempControlledCircuit.png| 200 px]]
+
The JFET has a characteristic curve that is similar to the bi-polar transistor. In the case of the bi-polar transistor you saw a dependence of the collector current (<math>I_C</math>) on the potential difference between the collector and the emitter (<math>V_{CE}</math>) for several values of the base current <math>I_B.</math>
  
 +
The JFET has a similar characteristic curve which the drain current (<math>I_D</math>) depends on the voltage difference between the drain and source (<math>V_{DS}</math>) for several values of the gate-source potential difference (<math>V_{S}</math>).
  
Let's add an input current for the base.
+
The difference is that higher base current in the bi-polar transistor yields higher output currents whereas in the JFET you get higher output currents with the least negative gate bias (n-channel).
  
==Setting I_B==
 
  
[[File:TF_EIM_TansAmp_1.png | 400 px]]
+
[[File:TF_EIM_JFET_Vgs-vs-Id.png | 300 px]][[File:TF_EIM_JFET_Vds-vs-Id.png | 300 px]]
  
In the above circuit there is a DC bias voltage and an AC input.  (The pulse generator in your lab has a DC offset you can use with the AC output sine wave).
+
= Equivalent circuit=
  
In you lab you will want to set an<math> I_B</math> using the DC bias <math>V_{bias}</math>  and a <math>V_{CC}</math> in order to put you in the middle of a load line.  The AC input will move along that load line.
+
The method of Equivalent circuits seeks to describe the performance of a circuit in terms of it input and output voltages and currents.  One you know the dependence of these parameters then the circuit becomes a black box.
  
Applying Kirchoff's loop theorem on the left loop I would have
 
  
:<math>V_{in} -I_BR_B- V_{BE} - I_ER_E = 0</math>
 
  
I have combined the DC bias and the AC input to a total input voltage V_{in}
+
Let
  
Since
+
<math>V_{in}, V_{out}, I_{in}, I_{out}</math> be the four variables which describe the circuit.
:: <math>I_E = (\beta + 1) I_B</math>
 
  
:<math>V_{in} - V_{BE} = I_B \left (R_B + \left (\beta +1 \right) R_E\right )</math>
+
choose
  
:<math>\Rightarrow I_B = \frac{V_{in} - V_{BE} }{R_B + \left (\beta +1 \right)R_E}</math>
+
<math>V_{in}</math> and <math>V_{out}</math> as the independent variables which will be described by the dependent variables <math>I_{in}</math> and <math>I_{out}</math>
  
 +
In other words you express the currents as functions of the voltages
  
If you know
+
:<math>I_{in} = f_{in}(V_{in},V_{out})</math>
 +
:<math>I_{in} = f_{out}(V_{in},V_{out})</math>
  
:<math>V_{BE} \approx 0.6 Volts </math>
 
  
and
+
using the chain rule you can express small changes in the current as
  
:<math>R_E = 220 \Omega</math>
+
:<math>\Delta I_{in} = \left ( \frac{\partial I_{in}}{\partial V_{in}} \right ) \Delta V_{in} + \left (  \frac{\partial I_{in}}{\partial V_{out}} \right ) \Delta V_{out}</math>
 +
:<math>\Delta I_{out} = \left ( \frac{\partial I_{out}}{\partial V_{in}} \right ) \Delta V_{in} + \left (  \frac{\partial I_{out}}{\partial V_{out}} \right ) \Delta V_{out}</math>  
  
Then you can set <math>I_B</math> using <math>R_B</math> for a given range of<math> V_{in}</math>
+
;Note:The derivatives with respect to one voltage are taken for fixed values of the other voltage.
  
If you re-derive the load line equation considering the additional resistor R_E then
 
  
Kirchoff's law
+
You define the derivative in terms of "y-parameters" such that
  
:<math>V_{CC} - I_CR_C - V_{CE} - I_ER_E = 0</math>
+
:<math>y_{is} \equiv \left ( \frac{\partial I_{in}}{\partial V_{in}} \right )</math> = input conductance
  
assume <math>I_C \approx I_E</math>
+
: <math>y_{rs} \equiv  \left (  \frac{\partial I_{in}}{\partial V_{out}} \right )</math>  
  
:<math>I_C = \frac{V_CC}{R_C+R_B} - \frac{1}{R_C+R_B}V_CE</math>
+
: <math>y_{fs} \equiv  \left ( \frac{\partial I_{out}}{\partial V_{in}} \right )</math>
  
[[File:TF_EIM_LoadLineEqFig.gif | 400 px]]
+
: <math>g_m \equiv y_{os} \equiv  \left ( \frac{\partial I_{out}}{\partial V_{out}} \right )</math> = output conductance
  
;Note
 
  
In the actual circuit<math> R_B</math> is replaced by  2 resistors (<math>R_1</math> and <math>R_2</math>) that provide the input bias voltage by forming a voltage divider using <math>V_{CC}</math>.
+
In the case of the common source JFET configuration
  
:<math>\frac{1}{R_B} = \frac{1}{R_1} + \frac{1}{R_2}</math>
+
<math>I_{in} = I_G</math> , <math>I_{out} = I_D</math>
  
In other words
+
==admittance==
  
:<math>V_{Bias} = \frac{R_2}{R_1 + R_2} V_{CC}</math>
+
;Notice: The above y-parameters have units of inverse Ohms 
  
== Determining R_E ==
+
The SI unit for this is called the "siemens" and is represented by '''S'''
  
[[File:TF_EIM_FindR_E_TransAmp.png | 200 px]]
+
:<math>\mbox {siemens} = S = \frac{1}{\mbox {Ohms}} = \Omega^{-1}</math>
  
Using Kirchoff's loop theorem again
+
The inverse of resistance is conductance. 
  
:<math>V_{bias} - I_BR_B + I_{CBO}R_B - V{BE} -I_ER_E = 0</math>
+
In electric engineering the term "admittance" is used to describe how easily a circuit will allow current to flow (its conductance).
  
:<math>I_B =(1-\alpha)I_E</math>
+
The unit "mho" is also used as an equivalent unit to '''S''' used by electrical engineers.
:<math>I_E = \frac{(I_C - I_{CBO})}{\alpha}  =  \frac{(I_C - I_{CBO})}{\frac{\beta}{\beta+1}}</math>
 
  
: <math>V_{bias} - V_{BE} = (I_B - I_{CBO}) R_B + I_E R_E</math>
 
:: <math>= (1-\alpha)I_ER_B +I_ER_E - I_{CBO} R_B</math>
 
:: <math>= (1-\frac{\beta}{\beta+1})I_E R_B  +I_ER_E - I_{CBO} R_B</math>
 
:: <math>= \left (\frac{1}{\beta+1} \right )\frac{\beta+1}{\beta} (I_C - I_{CBO})R_B  +I_ER_E - I_{CBO} R_B</math>
 
:: <math>=\frac{1}{\beta} (I_C - I_{CBO})R_B  +\frac{\beta+1}{\beta} (I_C - I_{CBO})R_E - I_{CBO} R_B</math>
 
  
:: <math>=\left ( \frac{1}{\beta}R_B  +\frac{\beta+1}{\beta}  R_E \right ) I_C + \left ( -\frac{1}{\beta}R_B  -\frac{\beta+1}{\beta} R_E - R_B \right )I_{CBO} </math>
+
:<math>\mbox {mho} = \frac{1}{\mbox {Ohms}} = \Omega^{-1}</math>
  
:<math>\Rightarrow \left ( \frac{1}{\beta}R_B  +\frac{\beta+1}{\beta}  R_E \right ) I_C = \left (V_{bias} - V_{BE} \right ) + \left ( \frac{1}{\beta}R_B  +\frac{\beta+1}{\beta} R_E + R_B \right )I_{CBO}</math>
 
  
== General Observations==
+
== the JFET equivalent Circuit==
  
1.) Notice the input goes through a high pass filter with a break point of<math> \frac{1}{R_1 C_1}</math>.  
+
Below is a common source JFET configuration. The Gate and Drain have the Source line as a common reference.  This is analogous to the common emitter configuration discussed in the last chapter and using in [[Lab_14_TF_EIM]].
  
2.) The output also goes through a high pass filter  with a break point of<math> \frac{1}{R_l C_2}</math>.
+
[[File:TF_EIM_JFET_CommonSOurceCircuit.png| 200 px]]
  
3.) Kirchoff voltage rule
 
  
:<math>V_{CC} -I_C R_C - V_{CE} - I_E R_E = 0</math>
+
===DC===
:<math>V_{CC} - V_{CE} -I_C (R_C  + R_E) = 0</math>  <math>I_C \approx I_E</math>
 
  
:<math>\Rightarrow I_C =\frac{ V_{CC} - V_{CE}}{R_C  + R_E }</math>
+
[[File:TF_EIM_JFET_DCequivCircuit.png| 200 px]]
  
4.) Kirchoff law
 
  
:<math>V_{CC} -(I_B + I_D) R_2 - V_{EB} - I_E R_E = 0</math>
+
The arrows with circles indicate ideal current sources.  The one on the left has the current <math>y_{rs}V_{out}</math> and the one on the right <math>y_{rs}V_{in}</math>
  
5.) INput resistance
+
===AC===
 +
[[File:TF_EIM_JFET_ACequivCircuit.png| 200 px]]
  
<math>\frac{1}{R_{in}} = \frac{1}{X_B} + \frac{1}{R_1} + \frac{1}{R_2}</math>
+
C_{gs} is the capacitance between the gate and the source.
  
6.)
+
C_{gd}  is the capacitance between the gate and the drain.
  
:<math>V_B = \frac{R_1}{R_1+R_2} V_{CC}</math>
+
=MOSFET=
 +
 
 +
MOSFET<math> \equiv</math> Metal-Oxide-Semiconductor Field Effect Transistor
  
 
[[Forest_Electronic_Instrumentation_and_Measurement]]
 
[[Forest_Electronic_Instrumentation_and_Measurement]]

Latest revision as of 15:00, 6 April 2011

Field Effect Transistors (FET, JFET, MOSFET)

Properties

FETs differ from the bipolar transistors in the las chapter in that the current from a FET is only due to the majority charge carriers in the semiconductor while bi-polar transistors current is produced from both carrier types; electron and hole.

  • higher input impedance than bi-polar
  • less gain than bi-polar
  • better temperature stability

JFET

JFET [math]\equiv[/math] Junction Field Effect Transistor


In a bi-polar transistor you have a depletion region with mixed charge carriers

TF EIM BipolarJunction.png TF EIM BipolarJunctionDiodeRep.png TF EIM BipolarJunctionCircuit.png
pnp bi-polar transistor Equivalence circuit Circuit diagram


In the Junction Field Effect Transistor you have a single charge carrier with the minority charge carriers forming a choke point for the majority carrier current flow. It is similar to "pinching" a garden hose when water is flowing through it.


TF EIM JFETnchan.gif TF EIM nchanDiodeRep.jpg TF EIM JFETnchanCircuit.jpeg
JFET Equivalence circuit Circuit diagram

The semiconductor material of the gate is the opposite of the channel. Here the n-p (or p-n) junction is between the gate and the channel.

The JFET operates by reverse biasing the gate-channel junction (diode) so the gate current doesn't flow in the direction indicated by the circuit diagram symbol. This means that the current through the gate is small (nAmps). As a result the input impedance looking into the gate is high (M[math]\Omega[/math]) for the equivalent circuit.

The current junction rule is

[math]I_D = I_S + I_G \approx I_S[/math]

for the Bi-Polar transistor

[math]I_C=I_E +I_B \approx I_E[/math]

Resistance

The FET acts like a resistor.

Consider the following circuit

Let

[math]V_{DD} =[/math] the drain driving voltage

[math]R_D[/math] = resistor between the drain and V_{DD}

if [math]\rho[/math] = resistivity of the n-type semiconductor

then

r = [math]\rho \frac{\ell}{A}[/math] = resistance of the JFET
[math]I_D = \frac{V_{DD}}{r+R_D}[/math]

If you reverse bias the gate then the depletion region at the p-n junction expands into the n-type material thereby reducing the cross-sectional area (A) of the channel.

FET pinchoff

If you continue to reverse bias the gate, keeping V_{DD} constant, then the drain current will decrease as you make the gate more negative.

The pinchoff condition will occur when the reverse bias is large enough to stop the drain current I_D.

[math]V_{GS(off)} = \mbox{pinchoff bias} = \frac{enT}{8 \epsilon}[/math]

where

[math]\epsilon[/math] = dielectric constant
[math]T[/math] = thickness of the channel
[math]n[/math] = number of impurity atoms per volume


You can find the "pinchoff" voltage by making V_{GS} more negative (n-channel) until the drain current I_D becomes zero.


In the other extreme

[math]I_{DSS} \equiv[/math] Maximum drain current (current flows from Drain to Source with the gate Shorted; ie [math]V_{GS}[/math] = 0)

Temperature

Because of the way a JFET operates, by pinching the current, the device heats up less at higher currents because you are no longer restricting the current flow.

At low values of[math] I_D[/math] and increase in the device temperature will cause an increase in [math]I_D[/math].

But at high values of [math]I_D[/math] the increase in temperature decreases [math]I_D[/math].

This feature of the JFET allows you to chain several together for amplification such that if one starts to overheat it will amplify less.

Characteristic curve

The JFET has a characteristic curve that is similar to the bi-polar transistor. In the case of the bi-polar transistor you saw a dependence of the collector current ([math]I_C[/math]) on the potential difference between the collector and the emitter ([math]V_{CE}[/math]) for several values of the base current [math]I_B.[/math]

The JFET has a similar characteristic curve which the drain current ([math]I_D[/math]) depends on the voltage difference between the drain and source ([math]V_{DS}[/math]) for several values of the gate-source potential difference ([math]V_{S}[/math]).

The difference is that higher base current in the bi-polar transistor yields higher output currents whereas in the JFET you get higher output currents with the least negative gate bias (n-channel).


TF EIM JFET Vgs-vs-Id.pngTF EIM JFET Vds-vs-Id.png

Equivalent circuit

The method of Equivalent circuits seeks to describe the performance of a circuit in terms of it input and output voltages and currents. One you know the dependence of these parameters then the circuit becomes a black box.


Let

[math]V_{in}, V_{out}, I_{in}, I_{out}[/math] be the four variables which describe the circuit.

choose

[math]V_{in}[/math] and [math]V_{out}[/math] as the independent variables which will be described by the dependent variables [math]I_{in}[/math] and [math]I_{out}[/math]

In other words you express the currents as functions of the voltages

[math]I_{in} = f_{in}(V_{in},V_{out})[/math]
[math]I_{in} = f_{out}(V_{in},V_{out})[/math]


using the chain rule you can express small changes in the current as

[math]\Delta I_{in} = \left ( \frac{\partial I_{in}}{\partial V_{in}} \right ) \Delta V_{in} + \left ( \frac{\partial I_{in}}{\partial V_{out}} \right ) \Delta V_{out}[/math]
[math]\Delta I_{out} = \left ( \frac{\partial I_{out}}{\partial V_{in}} \right ) \Delta V_{in} + \left ( \frac{\partial I_{out}}{\partial V_{out}} \right ) \Delta V_{out}[/math]
Note
The derivatives with respect to one voltage are taken for fixed values of the other voltage.


You define the derivative in terms of "y-parameters" such that

[math]y_{is} \equiv \left ( \frac{\partial I_{in}}{\partial V_{in}} \right )[/math] = input conductance
[math]y_{rs} \equiv \left ( \frac{\partial I_{in}}{\partial V_{out}} \right )[/math]
[math]y_{fs} \equiv \left ( \frac{\partial I_{out}}{\partial V_{in}} \right )[/math]
[math]g_m \equiv y_{os} \equiv \left ( \frac{\partial I_{out}}{\partial V_{out}} \right )[/math] = output conductance


In the case of the common source JFET configuration

[math]I_{in} = I_G[/math] , [math]I_{out} = I_D[/math]

admittance

Notice
The above y-parameters have units of inverse Ohms

The SI unit for this is called the "siemens" and is represented by S

[math]\mbox {siemens} = S = \frac{1}{\mbox {Ohms}} = \Omega^{-1}[/math]

The inverse of resistance is conductance.

In electric engineering the term "admittance" is used to describe how easily a circuit will allow current to flow (its conductance).

The unit "mho" is also used as an equivalent unit to S used by electrical engineers.


[math]\mbox {mho} = \frac{1}{\mbox {Ohms}} = \Omega^{-1}[/math]


the JFET equivalent Circuit

Below is a common source JFET configuration. The Gate and Drain have the Source line as a common reference. This is analogous to the common emitter configuration discussed in the last chapter and using in Lab_14_TF_EIM.

TF EIM JFET CommonSOurceCircuit.png


DC

TF EIM JFET DCequivCircuit.png


The arrows with circles indicate ideal current sources. The one on the left has the current [math]y_{rs}V_{out}[/math] and the one on the right [math]y_{rs}V_{in}[/math]

AC

TF EIM JFET ACequivCircuit.png

C_{gs} is the capacitance between the gate and the source.

C_{gd} is the capacitance between the gate and the drain.

MOSFET

MOSFET[math] \equiv[/math] Metal-Oxide-Semiconductor Field Effect Transistor

Forest_Electronic_Instrumentation_and_Measurement