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Chapter 1


Purpose and Scope

This thesis describes a system capable of digitally recording the analog charge deposited on position correlated charge collectors in the Region 1 tracking system detectors used by the Qweak experiment at Jefferson Lab (JLab). Ionizing particles traversing the R1 detector liberate electrons in the chamber gas. The free electrons are directed towards a charge collector by an applied external electric field. A preamplifier within the detector, known as a Gas Electron Multiplier (insert Sauli reference), will liberate about 100 electrons for every electron which passes through the preamplifier region. The GEM preamplifier uses the same avalanche principle which is the basis of a drift chamber detector. The final stage of this GEM detector contains analog voltage signals on individual copper strips. The analog signals on these individual strips are processed by a custom-made integrated circuit (IC) containing pre-amplifiers and pulse-shaping networks. A digital hit/no hit comparison is based on a programmable threshold voltage after the accumulated charge passes through these pre-amplifiers and pulse-shaping networks. These ICs were developed by the European Center for Nuclear Research (CERN) and have the ability to digitize the analog signal on 128 strips simultaneously. These cards will hereafter be referred to as VFAT cards.[1][2][3] The VFATs’ discriminators used to identify charge levels are also programmable via the VFATs’ registers. All of the programmable registers of the VFAT cards are accessed using an I2C interface.

The digital output of several VFAT cards is recorded using the V1495 VME module built by CAEN which operates on the VME backplane.[4] The V1495 module contains two Field-Programmable Gate Arrays (FPGA). The first FPGA is programmable by the user and is used as the main interface to the external I/Os on the faceplate of the V1495 The second FPGA controls the interfacing of the User FPGA and the VME backplane. Both FPGAs are members of the Cyclone device family.[5] The complete operation and underpinnings of the V1495 by itself are worthy of a separate thesis; the Cyclone Device Handbook, Volume 1, contains 385 pages. Of this, an understanding of perhaps 10 percent is sufficient to comprehend, operate, and effectively alter the properties of the Cyclone FPGA for the Region 1 detector.

Where necessary, this thesis will reference and attempt to explain other portions from various manuals. For the user firmware and the ROC (Read Out Controller) portions of the detector, UML diagrams have been included to simplify the process of familiarizing the reader with this detector and its respective data acquisition algorithms for the VFATs. Unfortunately, due to the finite nature of this thesis there are many assumptions that are made about the level of technical proficiency of the reader; hopefully, these are minimal, but certainly they are unavoidable.

The main portion of this thesis begins where the analog voltage signals exit the GEM detectors and ends where the data are sent from the ROC to a host computer . Many of the topics for which discussion is necessary to understand the full scope of this project will be briefly touched upon in this introduction.

Region 1 Detector Description

VFAT2 Readout Card


T1 Command Interpreter

SRAM and Hit Report Database

I2C Communication

Gumstix Microcontroller

Readout Controller (ROC)