TF EIM Chapt6

Field Effect Transistors (FET, JFET, MOSFET)

Properties

FETs differ from the bipolar transistors in the las chapter in that the current from a FET is only due to the majority charge carriers in the semiconductor while bi-polar transistors current is produced from both carrier types; electron and hole.

• higher input impedance than bi-polar
• less gain than bi-polar

JFET

JFET [math]\equiv[/math] Junction Field Effect Transistor

In a bi-polar transistor you have a depletion region with mixed charge carriers

pnp bi-polar transistor	Equivalence circuit	Circuit diagram

In the Junction Field Effect Transistor you have a single charge carrier with the minority charge carriers forming a choke point for the majority carrier current flow. It is similar to "pinching" a garden hose when water is flowing through it.

JFET	Equivalence circuit	Circuit diagram

The semiconductor material of the gate is the opposite of the channel. Here the n-p (or p-n) junction is between the gate and the channel.

The JFET operates by reverse biasing the gate-channel junction (diode) so the gate current doesn't flow in the direction indicated by the circuit diagram symbol. This means that the current through the gate is small (nAmps). As a result the input impedance looking into the gate is high (M[math]\Omega[/math]) for the equivalent circuit.

The current junction rule is

[math]I_D = I_S + I_G \approx I_S[/math]

for the Bi-Polar transistor

[math]I_C=I_E +I_B \approx I_E[/math]

Resistance

The FET acts like a resistor.

Consider the following circuit

Let

[math]V_{DD} =[/math] the drain driving voltage

[math]R_D[/math] = resistor between the drain and V_{DD}

if [math]\rho[/math] = resistivity of the n-type semiconductor

then

r = [math]\rho \frac{\ell}{A}[/math] = resistance of the JFET

[math]I_D = \frac{V_{DD}}{r+R_D}[/math]

If you reverse bias the gate then the depletion region at the p-n junction expands into the n-type material thereby reducing the cross-sectional area (A) of the channel.

FET pinchoff

If you continue to reverse bias the gate, keeping V_{DD} constant, then the drain current will decrease as you make the gate more negative.

The pinchoff condition will occur when the reverse bias is large enough to stop the drain current I_D.

[math]V_{GS(off)} = \mbox{pinchoff bias} = \frac{enT}{8 \epsilon}[/math]

where

[math]\epsilon[/math] = dielectric constant

[math]T[/math] = thickness of the channel

[math]n[/math] = number of impurity atoms per volume

[math]I_{DSS} \equiv[/math] Maximum drain current (current flows from Drain to Source with the gate Shorted; ie [math]V_{GS}[/math] = 0)

MOSFET

MOSFET[math] \equiv[/math] Metal-Oxide-Semiconductor Field Effect Transistor

Forest_Electronic_Instrumentation_and_Measurement