Difference between revisions of "Readout Electronics"

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  echo "e 134 0 on e 134 1 off e 134 2 on" | flipbit.arm
 
  echo "e 134 0 on e 134 1 off e 134 2 on" | flipbit.arm
  
4.)  send MClock pulses to look at output by using the SIS3610 to output a stream of LVDS pulses to the VFAT and look at DataOut
+
4.)  set VCAL
 +
 
 +
this turns one of the 8 bits to the calibration voltage Vcal  (It ranges from 1.074 to 0.877 Volts)
 +
 
 +
echo "e 129 1 on" | flipbit.arm
 +
 
 +
 
 +
5.) send MClock pulses to look at output by using the SIS3610 to output a stream of LVDS pulses to the VFAT and look at DataOut
  
 
=== set injected voltage===
 
=== set injected voltage===
  
 
# set VCal
 
# set VCal

Revision as of 11:07, 3 September 2008

I/O

Inputs to breakout box

Trigger (LVDS)
Clock ( RF synced pulse 31 MHz = 499/16 MHz, LVDS)
Flip Flop scaner (1 TTL pulse)


V1495 :

28 Pin output on 34 pin ribbon cables
Inputs to V1495:
180 bits of data = 12 bits Bunch Counter ( =31 MHz clock) + 12 bit (Event Counter + flags) + 12 bits (Chip ID) + 128 bits (data) + 16 bits (Checksum)
The input register has been set to a size of 256 bit and there are 12 of them
[math]\Rightarrow \frac{0.5 kbytes}{s}[/math]

Timing

VFAT:
Progammable through the Latency register (8 bits = 256 bits) you have but only 128 registers data registers. We can go back in time 100 *32 ns = 3 micro seconds. But we only may need 100 ns.

V1495: can have programmable delay up to?

We can program delays and play with the timing by downloading values for "lat" into the VFAT extended register and set delay on the V1495 through the ROC.


The V1495 can also interupt the VME backplane telling a ROC to readout the planes.

FPGA to VME data transfer

On 2/15/07 Ben Royd tested the read and write speeds between the VPM backplane and the FPGA user registers. He was able to write 16 bits to USER FPGA in 330 ns.

[math]\Rightarrow \frac{16 bits}{330 ns}\times \frac{1 byte}{8 bits} \times \frac{10^9 s}{ns} \approx 6\frac{Mbytes}{s}[/math]

VFAT controls

Brian Oborn: 282- 6243

VFAT control registers

Control register 0

bit bit name Function
0 Sleep/Run 0 = sleep, 1=run also reffereed to as sleep blocking

Control Register 1


Control register 2

Cal pulse Procedure

calibrate the circuit response

1.) Connect CalOut to DCU by setting DACsel = 1001

echo "p 65 0 on p 65 1 off p 65 2 off p 65 3 on" | flipbit.arm

2.) set calibration mode to output VCal values by setting CalMode = 01

echo "p 64 6 on p 64 7 off p " | flipbit.arm

3.) set the DAC and monitor how the output changes by setting TrimDAC = a five bit value


For channel 1 set TrimDAC= 1000 ( TrimDAC(4) =1 all others zero)

echo "e 1 1 off e 1 2 off e 1 3 off e 1 4 on" | flipbit.arm 

set everything off

echo "e 1 1 off e 1 2 off e 1 3 off e 1 4 off" | flipbit.arm 


for channel 128

echo "e 128 4 on" | flipbit.arm 

We may need to change the TrimDAC range

echo "e 134 0 on e 134 1 off e 134 2 on" | flipbit.arm

4.) set VCAL

this turns one of the 8 bits to the calibration voltage Vcal (It ranges from 1.074 to 0.877 Volts)

echo "e 129 1 on" | flipbit.arm


5.) send MClock pulses to look at output by using the SIS3610 to output a stream of LVDS pulses to the VFAT and look at DataOut

set injected voltage

  1. set VCal