JLab has built their own Flash ADC (called the F250)

It has a mini trigger connector which requires another VME board to convert from the standard lemo input to this mini input.

Addressing

JLab's F250 flash ADC will be used to measure the NaI output

ADdress is

Address
Pin	Switch	bit
A12	on/closed	0
A13	on	0
A14	on	0
A15	on	0
A16	on	0
A17	off/open	1
A18	off	1
A19	off	1
A20	on	0
A21	off	1
A22	off	1
A23	off	1

Module address = 0xee0000 = 111011100000000000000000 d

If I want 0xaa0000 = 101010100000000000000000 d

If I want 0xbb = 10111011

Address
Pin	Switch	bit
A12	on/closed	0
A13	on	0
A14	on	0
A15	on	0
A16	off	1
A17	off/open	1
A18	on	0
A19	off	1
A20	off	1
A21	off	1
A22	on	0
A23	off	1

check status

-> faStatus(0)

STATUS for FADC in slot 4 at base address 0x90bb0000 
-------------------------------------------------- 
 Board Firmware Rev/ID = 0x0114 : ADC Processing Rev = 0x0909
 Alternate VME Addressing: Multiblock Disabled
   A32 Enabled at VME base 0x08000000 or CPU addr 0x80000000

 Signal Sources: 
   Ref Clock : Internal
   Trig Src  : Front Panel (Async)
   Sync Reset: VME (Software)

 Configuration: 
   Internal Clock ON
   Bus Error DISABLED
   MultiBlock transfer DISABLED
   Software Sync Reset ENABLED

 ADC Processing Configuration: (0x0040 0x0040)
   Channel Disable Mask = 0x0000
   Resolution           = 10 bits
   Mode = 1  (Disabled)
   Lookback (PL)    = 0 ns   Time Window (PTW) = 64 ns
   Time Before Peak = 0 ns   Time After Peak   = 0 ns
   Max Peak Count   = 4 

  CSR       Register = 0x006318e0
  Control 1 Register = 0x00030e1f 
  Control 2 Register = 0x00000000 - Disabled
  Internal Triggers (Live) = 0
  Trigger   Scaler         = 0
  Events in FIFO     = 0  (Block level = 1)
value = 44 = 0x2c = ','

Software Trigger

Initialize FADC for software trigger mode

Initialize the FADC so it will accept software triggers.

faInit(0xbb0000,0,0,0)

-> faInit(0xbb0000,0,0,0) Initialized FADC 0 Slot # 4 at address 0x90bb0000 faInit: Enabling FADC Internal Clock, and Software Triggers (Soft Sync Reset) value = 0 = 0x0

Notice FADC ID is 0 in Slot 4

define processing mode=

int
faSetProcMode(int id, int pmode, unsigned int PL, unsigned int PTW,
	      unsigned int NSB, unsigned int NSA, unsigned int NP, int bank)


An example of this should be in one of the Readout lists, however, right now there are 3 viable processing modes (pmode =1,2 or 3)

pmode = 1  RAW Window mode: all samples within PTW are saved
pmode = 2  RAW Pulse mode: NSA+NSB+1 samples around a threshold crossing
                          are saved.
pmode = 3  Integral pulse mode: NSA+NSB+1 samples are summed and the sum
          along with the timestmp for the threshold crossing are saved.

faSetProcMode(4,1,40,38,3,6,1,0)

check using the status command


-> faStatus(0)             

STATUS for FADC in slot 4 at base address 0x90bb0000 
-------------------------------------------------- 
 Board Firmware Rev/ID = 0x0114 : ADC Processing Rev = 0x0909
 Alternate VME Addressing: Multiblock Disabled
   A32 Enabled at VME base 0x08000000 or CPU addr 0x80000000

 Signal Sources: 
   Ref Clock : Internal
   Trig Src  : VME (Software)
   Sync Reset: VME (Software)

 Configuration: 
   Internal Clock ON
   Bus Error DISABLED
   MultiBlock transfer DISABLED
   Software Triggers   ENABLED
   Software Sync Reset ENABLED

 ADC Processing Configuration: (0x0040 0x0040)
   Channel Disable Mask = 0x0000
   Resolution           = 10 bits
   Mode = 1  (Disabled)
   Lookback (PL)    = 0 ns   Time Window (PTW) = 64 ns
   Time Before Peak = 0 ns   Time After Peak   = 0 ns
   Max Peak Count   = 4 

  CSR       Register = 0x006318e0
  Control 1 Register = 0x00030eef 
  Control 2 Register = 0x00000000 - Disabled
  Internal Triggers (Live) = 0
  Trigger   Scaler         = 0
  Events in FIFO     = 0  (Block level = 1)
value = 44 = 0x2c = ','
->

 Trig Src  : VME (Software)

Set the internal trigger pulse width

set the internal trigger pulse width to 2 clock ticks (8 ns)

/*                                                                                                                             
 * Set Internal trigger pulse width and deadtime between triggers                                                              
 *   Range for each :   4ns <-> 1020ns                                                                                         
 *                                                                                                                             
*    Units are in clock ticks  (4ns/tick)                                                                                      
 */

faItrigControl(int id, unsigned short itrig_width, unsigned short itrig_dt)

-> faItrigControl(0, 2, 0 )
value = 131082 = 0x2000a

Enable all channels


-> faEnable(0,0,0)

Generate a software trigger

-> faTrig(0)
value = -1866792960 = 0x90bb0000 = tclOpenFiles + 0x82ef31a0

check if there is an event in the FIFO


-> faStatus(0)    
STATUS for FADC in slot 4 at base address 0x90bb0000 
-------------------------------------------------- 
 Board Firmware Rev/ID = 0x0114 : ADC Processing Rev = 0x0909
 Alternate VME Addressing: Multiblock Disabled
   A32 Enabled at VME base 0x08000000 or CPU addr 0x80000000

 Signal Sources: 
   Ref Clock : Internal
   Trig Src  : VME (Software)
   Sync Reset: VME (Software)

 Configuration: 
   Internal Clock ON
   Bus Error DISABLED
   MultiBlock transfer DISABLED
   Software Triggers   ENABLED
   Software Sync Reset ENABLED

 ADC Processing Configuration: (0x0040 0x0040)
   Channel Disable Mask = 0x0000
   Resolution           = 10 bits
   Mode = 1  (Disabled)
   Lookback (PL)    = 0 ns   Time Window (PTW) = 64 ns
   Time Before Peak = 0 ns   Time After Peak   = 0 ns
   Max Peak Count   = 4 

  CSR       Register = 0x006318e3
  Control 1 Register = 0x00030eef 
  Control 2 Register = 0x00000007 - Enabled for triggers
  Internal Triggers (Live) = 0
  Trigger   Scaler         = 1
  Events in FIFO     = 1  (Block level = 1) - Data Available
  RAM Level (Bytes)  = 0 
value = 26 = 0x1a
->

Now I see an event in the FIFO

Print FIFO status

-> faPrintFifoStatus(0)
Fifo Buffers Status (DataFlow Status = 0x0000013d
  Input Buffer : 0x90009000 
    FPGA1: wc=0   Empty=1 Full=0 Ready=1
    FPGA2: wc=0   Empty=1 Full=0 Ready=1
  Build Buffer : 0x10001000 
    FPGA1: wc=0   Empty=1 Full=0 
    FPGA2: wc=0   Empty=1 Full=0 
  Output Buffer: 0x20002000 
    FPGA1: wc=0   Empty=1 Full=0 
    FPGA2: wc=0   Empty=1 Full=0 
value = 34 = 0x22 = '"'

Count events ready to be readout

you can count how many events or blocks are ready to be read out with the command

-> faDready(0,0)
value = 1 = 0x1

try to read a block

-> faPrintBlock(0,0)
0xdbb7b90 (tShell): faReadEvent: ERROR: Invalid Header Word 0xf0000000
value = -1 = 0xffffffff

Documentation

Data Format

File:JLab F250 ADC V1.2 DataFormat.pdf

Readoutlist example

___________________________________________________________________
|                                                                   |
|  Jefferson Lab                      Tel:  (757) 269-7159          |
|  Riad Suleiman                      FAX:  (757) 269-5520          |
|  12050 Jefferson Ave                                              |
|  Suite 500                                                        |
|  Newport News, VA 23606             Email:suleiman@jlab.org       |
|  Text Pager: 7572893892@messaging.nextel.com                      |
|  http://www.jlab.org/~suleiman                                    |
|  Home: (757) 865-0355                                             |
-------------------------------------------------------------------

#  Source for generic VME readout using a
#  TJNAF trigger supervisor interface register (TIR)
#  as a source for external interrupts
#
#    David Abbott, TJNAF 1996

readout list VME1
maximum 16384,400
vme readout
#polling
#ts control


const TIR_ADDR = 0x0ed0
const FADC_ADDR = 0xee0000
const FADC_BLOCK_MODE = 1
const MAX_FADC_DATA = 4000

extern int bigendian_out;
extern int fadcID[20];
int FA_SLOT;


begin download

 variable res

# If the ROC is sending data to Little-Endian EB
# e.g. a x86 Linux CPU then bigendian_out = 0.
# Unless the ROC is also running on a Little-Endian
# machine. Then set bigendian_out=1.
 bigendian_out = 0;


# Setup TIR
 tirInit(TIR_ADDR);

# Initialize FADC library and Modules for standalone
# and Front Panel Triggers
faInit(FADC_ADDR,0,1,0xea13);
FA_SLOT = fadcID[0];

 log inform "User Download Executed"

end download

begin prestart

 log inform "Entering User Prestart"

 init trig source VME
 link async trig source VME 1 to usrtrig and usrtrig_done
 event type 1 then read VME 1

# Assume FADCs have been Initialized at boot or in download
# Setup FADC Programming
 faSetBlockLevel(FA_SLOT,1);
# for Block Reads
 faEnableBusError(FA_SLOT);
# for Single Cycle Reads
#  faDisableBusError(FA_SLOT);

# Set All channel thresholds to 0
 faSetThreshold(FA_SLOT,0,0xffff);


# Setup option 1 processing - RAW Window Data     <--
#       option 2            - RAW Pulse Data
#       option 3            - Integral Pulse Data
# Setup 120 nsec latency (PL  = 30) 
# Setup  80 nsec Window  (PTW = 20)
# Setup Pulse widths of 36ns (NSB(3)+NSA(6) = 9) 
# Setup up to 1 pulse processed
# Setup for both ADC banks(0 - all channels 0-15)
 faSetProcMode(FA_SLOT,1,40,38,3,6,1,0);


# Print out status
 faStatus(FA_SLOT,0);

 log inform "User Prestart Executed"

end prestart

begin end

 CDODISABLE(VME,1,0);

#FADC Disable
 faGDisable(0,0);

#FADC Event status - Is all data read out
 faStatus(FA_SLOT,0);

 log inform "User End Executed"

end end

begin pause

 CDODISABLE(VME,1,0);

 log inform "User Pause Executed"

end pause

begin go

 variable outval

 log inform "Entering User Go"

# Enable FADCs
 faGEnable(0,0);

 taskDelay(1);

# Send Sync Reset to FADC
 faSDC_Sync();

 taskDelay(1);

 CDOENABLE(VME,1,0);

end go

begin trigger usrtrig

variable ii, stat, csr

rol->dabufp = (long *) 0;
open event type EVTYPE of BT_UI4

%%
int nwrds=0;
/* Check if a Block of data is available */
for(ii=0;ii<100;ii++) {
   stat = faBready(FA_SLOT);
   if (stat>0) {
     *rol->dabufp++ = ii;
     break;
   }
}
if(stat > 0) {
  nwrds = faReadBlock(FA_SLOT,rol->dabufp,MAX_FADC_DATA,FADC_BLOCK_MODE);
  if(nwrds<=0) {
     logMsg("ERROR: FADC Block Read Failed - Status 0x%x\n",nwrds,0,0,0,0,0);
     *rol->dabufp++ = 0xda000bad;
     faClear(FA_SLOT);
  } else {
     rol->dabufp += nwrds;
  }
}else{
  *rol->dabufp++ = 0xfa000bad;
  logMsg("ERROR: NO data in FADC  datascan = 0x%x\n",stat,0,0,0,0,0);
  faClear(FA_SLOT);
}

/* Check that there is no data left */
 stat = faDready(FA_SLOT);
 if(stat>0) {
  csr = faReadCSR(FA_SLOT);
  logMsg("ERROR: Data still in FADC (event %d, scan 0x%x csr 0x%x ) - clearing\n",
	*(rol->nevents),stat,csr,0,0,0);
  faClear(FA_SLOT);
 }

%%

close event

end trigger

begin done usrtrig


end done


begin done

# Acknowledge tir register
 CDOACK(VME,1,0);

end done

begin status

end status