Difference between revisions of "CH HPGe Electronics Chain"

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HPGe → Split signal using BNC T junction
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='''Summer 2022 Efficiency Measuremets'''=
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 +
1. Output 1 of HPGe → fan in/out
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2A. 1st fan in/out output → spec amp
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 +
3A. Spec amp output → ADC input
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2B. 2nd fan in/out output → timing filter amp
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 +
3B. Timing filter amp output → discriminator input
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 +
4B. Discriminator output → negative input of gate/delay generator 1
  
First line to spec amp -> peak sensing ADC  
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5B. Negative output of gate/delay generator 1 → ADC Gate
  
Second line to timing/filter amp with ~2.3x amplification (also inverts)
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5C. Positive output of gate/delay generator 1 Positive input of gate/delay generator 2
  
Discriminator (Blue lecroy model #xxxx)
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6C. Negative output of gate/delay generator 2 Readout card port 1
  
→ Top of dual timer then into bottom of dual timer
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=='''Discriminator Settings'''==
  
→ Into 1st gate and delay generator
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Note that when using a timing filter amp, the effective level of discrimination is adjusted. The timing-filter amp used (table below) has a minimum amplification of ~2.3x. To keep things consistent with using the unaltered pre-amp signal from the HPGe detector, the threshold is divided by the gain set by the timing filter amp and will be referred to as the ''Effective Threshold''.
  
--> positive sent to second gate and delay module
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{| class="wikitable" border="2" style="text-align:center;" |cellpadding="20" cellspacing="1
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! Discriminator Threshold (mV) !! Gain !! Effective Threshold (mV)
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|-
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| 30.2 || N/A || 30.2
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|-
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| 30.2 || ~2.4 || 12.58
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|-
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| 30.4 || ~2.8 || 10.86
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|}
  
--> negative sent to PADC as gate for spec amp signal
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='''List of Modules'''=
  
→ 2nd gate and delay generator used for ROC signal
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{| class="wikitable" border="2" style="text-align:center;" |cellpadding="20" cellspacing="1
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|-
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! Module !! Brand !! Model Number
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|-
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| Fan in/out || CAEN || N625
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|-
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| Spec-Amp || Ortec || 672
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|-
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| ADC || CAEN || V785N
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|-
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| Timing Filter Amp || Ortec || 474
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|-
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| Discriminator || LeCroy || 821
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|-
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| Gate & Delay Generator 1 || Ortec || 416
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|-
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| Gate & Delay Generator 2 || Ortec || 416
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|-
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| Readout Controller || SIS GmbH || SIS3820
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|}
  
June 2022 Efficiency Measuremets
+
='''Past'''=
  
1. Output 1 fan in/out
+
HPGe Split signal using BNC T junction
  
2A. 1st fan in/out output → spec amp
+
First line to spec amp -> peak sensing ADC
  
3A. Spec amp output → ADC input
+
→ Second line to timing/filter amp with ~2.3x amplification (also inverts)
  
2B. 2nd fan in/out output timing filter amp
+
Discriminator (Blue lecroy model #xxxx)
  
3B. Timing filter amp output discriminator input
+
Top of dual timer then into bottom of dual timer
  
4B. Discriminator output negative input of gate/delay generator 1
+
Into 1st gate and delay generator  
  
5B. Negative output of gate/delay generator 1 → ADC Gate
+
--> positive sent to second gate and delay module
  
5C. Positive output of gate/delay generator 1 → Positive input of gate/delay generator 2
+
--> negative sent to PADC as gate for spec amp signal
  
6C. Negative output of gate/delay generator 2 → Readout card port 1
+
→ 2nd gate and delay generator used for ROC signal
  
 
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='''Previous Page'''=
 
='''Previous Page'''=
  
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[[PAS Feasibility Study Runs]]
 
[[PAS Feasibility Study Runs]]
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[[CH HPGe Efficiency]]

Latest revision as of 18:49, 27 July 2022

Summer 2022 Efficiency Measuremets

1. Output 1 of HPGe → fan in/out

2A. 1st fan in/out output → spec amp

3A. Spec amp output → ADC input

2B. 2nd fan in/out output → timing filter amp

3B. Timing filter amp output → discriminator input

4B. Discriminator output → negative input of gate/delay generator 1

5B. Negative output of gate/delay generator 1 → ADC Gate

5C. Positive output of gate/delay generator 1 → Positive input of gate/delay generator 2

6C. Negative output of gate/delay generator 2 → Readout card port 1

Discriminator Settings

Note that when using a timing filter amp, the effective level of discrimination is adjusted. The timing-filter amp used (table below) has a minimum amplification of ~2.3x. To keep things consistent with using the unaltered pre-amp signal from the HPGe detector, the threshold is divided by the gain set by the timing filter amp and will be referred to as the Effective Threshold.

Discriminator Threshold (mV) Gain Effective Threshold (mV)
30.2 N/A 30.2
30.2 ~2.4 12.58
30.4 ~2.8 10.86

List of Modules

Module Brand Model Number
Fan in/out CAEN N625
Spec-Amp Ortec 672
ADC CAEN V785N
Timing Filter Amp Ortec 474
Discriminator LeCroy 821
Gate & Delay Generator 1 Ortec 416
Gate & Delay Generator 2 Ortec 416
Readout Controller SIS GmbH SIS3820

Past

HPGe → Split signal using BNC T junction

→ First line to spec amp -> peak sensing ADC

→ Second line to timing/filter amp with ~2.3x amplification (also inverts)

→ Discriminator (Blue lecroy model #xxxx)

→ Top of dual timer then into bottom of dual timer

→ Into 1st gate and delay generator

--> positive sent to second gate and delay module

--> negative sent to PADC as gate for spec amp signal

→ 2nd gate and delay generator used for ROC signal


Previous Page

CaGaS Phase II

PAS Feasibility Study Runs

CH HPGe Efficiency