Difference between revisions of "CH 785NADC"
Latest revision as of 23:34, 7 September 2022
The signal conversion timing is shown in Fig. 2.2.. The diagram includes four different time ranges: idle, data acquisition, settling time, digitisation and clear. While the conversion logic is idle, the occurrence of a GATE pulse starts the acquiring data phase, during which the PEAK output increases according to the input signal until the first peak is reached. As the highest peak within the gate is reached, the peak value is held by means of the capacitor C1 until the end of the digital conversion (digitisation) which starts about 600 ns (settling time) after the end of the GATE signal and takes about 6 μs. After the digital conversion, the clear phase takes place by a fast capacitor discharge (about 600 ns) which makes the conversion logic idle again.