Readout Electronics

I/O

Inputs to breakout box

Trigger (LVDS)

Clock ( RF synced pulse 31 MHz = 499/16 MHz, LVDS)

Flip Flop scaner (1 TTL pulse)

V1495 :

28 Pin output on 34 pin ribbon cables

Inputs to V1495:

180 bits of data = 12 bits Bunch Counter ( =31 MHz clock) + 12 bit (Event Counter + flags) + 12 bits (Chip ID) + 128 bits (data) + 16 bits (Checksum)

The input register has been set to a size of 256 bit and there are 12 of them

[math]\Rightarrow \frac{0.5 kbytes}{s}[/math]

Timing

VFAT:

Progammable through the Latency register (8 bits = 256 bits) you have but only 128 registers data registers. We can go back in time 100 *32 ns = 3 micro seconds. But we only may need 100 ns.

V1495: can have programmable delay up to?

We can program delays and play with the timing by downloading values for "lat" into the VFAT extended register and set delay on the V1495 through the ROC.

The V1495 can also interupt the VME backplane telling a ROC to readout the planes.

FPGA to VME data transfer

On 2/15/07 Ben Royd tested the read and write speeds between the VPM backplane and the FPGA user registers. He was able to write 16 bits to USER FPGA in 330 ns.

[math]\Rightarrow \frac{16 bits}{330 ns}\times \frac{1 byte}{8 bits} \times \frac{10^9 s}{ns} \approx 6\frac{Mbytes}{s}[/math]

VFAT controls

VFAT control registers

Control register 0

bit	bit name	Function
0	Sleep/Run	0 = sleep, 1=run also reffereed to as sleep blocking

Control Register 1

Control register 2

Cal pulse Procedure

=== calibrate the circuit response

1. Connect CalOut to DCU

set DACsel = 1001

1. set calibration mode to output VCal values

set CalMode = 01

1. set the DAC and monitor how the output changes

set TrimDAC = a five bit value

1. send MClock pulses to look at output

use the SIS3610 to output a stream of LVDS pulses to the VFAT and look at DataOut

=== set injected voltage

1. set VCal