CH HPGe Electronics Chain
HPGe → Split signal using BNC T junction
→ First line to spec amp -> peak sensing ADC
→ Second line to timing/filter amp with ~2.3x amplification (also inverts)
→ Discriminator (Blue lecroy model #xxxx)
→ Top of dual timer then into bottom of dual timer
→ Into 1st gate and delay generator
--> positive sent to second gate and delay module
--> negative sent to PADC as gate for spec amp signal
→ 2nd gate and delay generator used for ROC signal
June 2022 Efficiency Measuremets
1. Output 1 → fan in/out
2A. 1st fan in/out output → spec amp
3A. Spec amp output → ADC input
2B. 2nd fan in/out output → timing filter amp
3B. Timing filter amp output → discriminator input
4B. Discriminator output → negative input of gate/delay generator 1
5B. Negative output of gate/delay generator 1 → ADC Gate
5C. Positive output of gate/delay generator 1 → Positive input of gate/delay generator 2
6C. Negative output of gate/delay generator 2 → Readout card port 1