CAEN V1495 IO
Manual
Media:CAEN_V1495_Manual_Rev6.pdf
Readout code
V1
The ZIP file below contains the HDL source code to download into the V1495
http://www.physics.isu.edu/~tforest/DAQ/GEMReadout_V1495Source_Rev1_0.zip
The ZIP file below contains the ROC library
http://www.physics.isu.edu/~tforest/DAQ/GEMReadout_VxWorkxSource_11_26_2008.zip
ROC lib
compile library
To compile the ROC library I executed the following command within the subdirectory containing the v1495.c file
ccppc -fno-builtin -fno-for-scope -fstrength-reduce -mlongcall -mcpu=604 -DCPU=PPC604 -DVXWORKS -D_GNU_TOOL -DVXWORKSPPC -I/usr/local/coda/2.5/common/include/ -I../h -c -o v1495Lib.o -i v1495.c
load library onto the ROC
I then copies the library v1495Lib.o into my ROC library subdirectory which is where the ROC is pooing at boot up
/home/daq/CODA/ROClibs/libs
I loaded the library by hand by typing the following at the ROC console
-> ld < v1495Lib.o value = 268430512 = 0xfffecb0
Setting address
The address pins on this module are not labeled so I adopted the convention of numbering them from left to right as I look from the front pannel.
| Address | |
| Pin | Setting |
| SW 3 | 0 |
| SW 4 | 8 |
| SW 7 | 1 |
| SW 8 | 1 |
probing memory
I set the switches as follows
sw3 sw4 sw7 sw8
0 8 1 1
And the following is a printout of my board:
(0x80118000 - A32 0x90118000 - A24)
-> m 0x80118000
80118000: 0000-
80118002: 0000-
80118004: 0000-
80118006: 00dd-
80118008: 001f-
8011800a: ffff-
8011800c: 0002-
8011800e: 0001-
80118010: 00ff-
80118012: 0001-
80118014: 00ff-
80118016: 0001-
80118018: 0000-
8011801a: ffff-.
value = 1 = 0x1
-> m 0x90118000
90118000: 0000-
90118002: 0000-
90118004: 0000-
90118006: 00dd-
90118008: 001f-
9011800a: ffff-
9011800c: 0002-
9011800e: 0001-
90118010: 00ff-
90118012: 0001-
90118014: 00ff-
90118016: 0001-
90118018: 0000-
9011801a: ffff-.
value = 1 = 0x1
->
v1495test function
The v1495 library has the function below which when
//v1495test()
int
v1495test(unsigned int baseaddr)
{
// the address location below starts at the USER FPGA access location which is
//0x8000 lower in memory than the dial switches for the module address location.
// if SW3=0 SW4=8 SW7=1 SW8=1 => 0x80118000 is the 32 bit address and 0x90118000 is the 24 bit adresss
// then try v1495test(0x80110000)
volatile V1495 *v1495 = (V1495 *) baseaddr;
unsigned short *data16 = (unsigned short *)&(v1495->control);
printf("Control [0x%08x] = 0x%04x\n",&(v1495->control),v1495->control);
printf("firmwareRev [0x%08x] = 0x%04x\n",&(v1495->firmwareRev),v1495->firmwareRev);
printf("selflashVME [0x%08x] = 0x%04x\n",&(v1495->selflashVME),v1495->selflashVME);
printf("flashVME [0x%08x] = 0x%04x\n",&(v1495->flashVME),v1495->flashVME);
printf("selflashUSER [0x%08x] = 0x%04x\n",&(v1495->selflashUSER),v1495->selflashUSER);
printf("flashUSER [0x%08x] = 0x%04x\n",&(v1495->flashUSER),v1495->flashUSER);
printf("configROM [0x%08x] = 0x%04x\n",&(v1495->configROM[0]),v1495->configROM[0]);
return(0);
}
example
-> v1495test(0x80110000); Control [0x80118000] = 0x0000 firmwareRev [0x8011800c] = 0x0003 selflashVME [0x8011800e] = 0x0001 flashVME [0x80118010] = 0x00ff selflashUSER [0x80118012] = 0x0001 flashUSER [0x80118014] = 0x00ff configROM [0x80118100] = 0x0065 value = 0 = 0x0
Download Firmware
To download the firmware to the USER FPGA area you need to pass the address which is 0x8000 below what the dial setting are
for example the dial settings are
| Address | |
| Pin | Setting |
| SW 3 | 0 |
| SW 4 | 8 |
| SW 7 | 1 |
| SW 8 | 1 |
Instead of the address of the control register (which corresponds to the dial settings) You need to pass the memory address of the USER FPGA access which is 0x8000 lower in memory
for example
v1495firmware(0x80110000,"GEMReadout.rbf",0,0)
and NOT v1495firmware(0x80118000,"GEMReadout.rbf",0,0)
it took about 10 minutes to download
-> v1495firmware(0x80110000,"GEMReadout.rbf",0,0);
********************************************************
* CAEN SpA - Front-End Division *
* ---------------------------------------------------- *
* Firmware Upgrade of the V1495 *
* Version 1.1 (27/07/06) *
* Sergey Boyarinov: CLAS version 23-Apr-2007 *
********************************************************
Updating firmware of the FPGA USER with the file GEMReadout.rbf
End of file: bp=33 bcnt=177705
Firmware loaded successfully. Written 177705 bytes
Reloading user FPGA firmware...done!
Using as a Trigger Supervisor
Subdirectories
in /home/daq/CODA/ROClibs/MiniTS
minits.c
in /home/daq/CODA/ROClibs/libs
V1495MiniTS.rbf V1495VME_rev_1.1.rbf
Load firmware
From the VXworks prompt load the firmware with the commands
v1495firmware(0xfa510000,"V1495MiniTS.rbf",0,0)
v1495firmware(0xfa510000,"V1495VME_rev_1.1.rbf",0,1)
Compile the MiniTS library
The Makefile
CCPPC=ccppc
INCLUDES=-fno-builtin -fno-for-scope -fstrength-reduce -mlongcall -mcpu=604 -DCP
U=PPC604 -DVXWORKS -D_GNU_TOOL -DVXWORKSPPC -I/usr/local/coda/2.5/common/include
/ -I../h -c
all:
$(CCPPC) $(INCLUDES) -o minits.o minits.c
Ben Raydo e-mail for MiniTS
Makefile
VxWorks makefile for minits.c (run 'make minits.o' to build...you may have to modify the makefile for the machine your building this on)
minits.c
Example usage for VxWorks using interrupts.
Alternatively you can run this in polling mode by:
1) calling MiniTSPollTrig() repeatedly to see if a trigger has been generated
2) when MiniTSPollTrig() = 1 readout your DAQ modules, then call MiniTSAck() to acknowledge trigger so another can be generated
V1495MiniTS.rbf
This is the USER FPGA code I put together for you. Be sure to load this to the USER space and not the VME one!
V1495VME_rev_1.1.rbf
This is the VME FPGA code from CAEN (32bit mode with interrupt support). Be sure to load this to the VME space.
After you load the "V1495VME_rev_1.1.rbf" VME FPGA and "V1495MiniTS.rbf" USER FPGA reboot your crate and check the following: 1) v1495 offset 0x800C contains the firmware revision of the VME FPGA and should be 1.1. You must do a 16bit read to check this. (if not make sure your STD/BKP jumper on the V1495 is set to the position you loaded the VME FPGA firmware to)
2) run 'MiniTS_Init <a24_addr>', where <a24_addr> should be the hexadecimal A24 address of your board. This function will verify that the USER FPGA is loaded.
Here's an example of what I get when I run this:
Command: -> MiniTS_Init 0x530000
Output: MiniTS_Init() started...
MiniTS A24 VME Address 0x00530000 mapped to CPU Address 0x90530000 MiniTS Id register = 0x4D495453
disconnecting vector 224 MiniTSId = 0x4D495453 FirmwareRev = 0x00010000 BoardId = 0x00000000 TriggerEn = 0x00000000 IntEn = 0x00000000 TriggerCnt = 0x00000000 TriggerStatus = 0x00000000 MiniTSSetupInt() MiniTSEnableTrig() Ready... TS_Interrupt received (1)... TS_Interrupt received (2)... TS_Interrupt received (3)... TS_Interrupt received (4)...
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