Warren Parsons MS Thesis

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Warren_Parsons_Log_Book


Introduction

The scope of this thesis is to enlighten the reader as to the inner workings of the Region 1 detector for the QWEAK experiment at Jefferson Laboratories; indeed, it can be considered to be the unofficial, de facto manual for this detector.

Try to alter the style a bit to be dryer

This thesis describes a system for recording the 
electronic signals from a detector used in the 
Region 1 tracking system for the QWEAK experiment 
at Jefferson Lab.

It is the aggregate of many different materials describing many different technologies all combined for this purpose. It is, therefore, not the intention of this thesis to intimately describe the inner workings of each and every one of these separate systems, nor is it a thorough description of other detectors in the QWEAK experiment or the physics behind the QWEAK experiment itself. It is but a guide through the systems comprising the Region 1 detector such that the reader will understand the essential components for proper comprehension and operation.

As an example, the FPGA for the v1495 user firmware is a member of the Cyclone device family. The complete operation and underpinnings of this device by itself are worthy of a separate thesis; just the Cyclone Device Handbook, Volume 1, contains 385 pages. Of this, an understanding of perhaps 10 percent is sufficient to comprehend, operator, and effectively alter the properties of the Cyclone FPGA for the Region 1 detector.

Where necessary this thesis will reference and attempt to explain other portions from various manuals; all of these pertinent manuals are included with the original copy of this thesis. For the user firmware and the ROC (Read Out Controller) portions of the detector, UML diagrams have been included to simplify the process of familiarizing oneself with this detector and its respective algorithms for data acquisition from the VFATs. Unfortunately, due to the finite nature of this thesis there are many assumptions that are made about the level of technical proficiency of the reader; hopefully, these are minimal, but certainly they are unavoidable.

The Region 1 detector is comprised of the following individual systems and each one is described in its own section.

VFAT readout card

Gumstick

I2C

V1495 User Firmware

GEMReadout.vhd

The main function routines?
GEMReadout_tb.vhd
GEMRxChannel.vhd

The following is the UML for the GEMRxChannel module:

File:GEMRxChannelUML.pdf

GEMRxEventDataFIFO.vhd
a routine controlling the FIFO
GEMRxEventSizeFIFO.vhd
Defines the Event size and structure
GEMTxChannel.vhd
PLLVBlock.vhd
spare_if_rtl.vhd
tristate_if_trl.vhd
v1495usr.vhd
v1495usr_pkg.vhd
GEMTrigger.vhd

The following is the UML diagram for the GEMTrigger module:

File:GEMTriggerUML.pdf

v1495usr_hal.vqm
From the v1495 manual this is the v1495 Hardware Abstraction Layer. It is an HDL module provided in Verilog format at the netlist level in order to help interface the hardware.
Reading through this file makes it clear that we are using the Cyclone chip family. I can't find where the "cyclone_lcell" module is defined. I am wondering if it is defined inside of the Quartus II program in a library somewhere. Figuring this out would probably help unravel how our HDL code is actually instantiated in hardware.

General introduction to the readout scheme

Readout Blockdiagram

Changing MCLK frequency

Output MCLK and Level 1 Trigger

VFAT input port

V1495 Data format

CODA Readout

The V1495 module transfers data 16 bits at a time to the ROC. An array within the ROC memory will be filled with the V1495 data stream 16 bits at a time to optimize data throughout. The array within the ROC memory will then be transferred to the host computer and stored.

ROC library

Readout list

CODA Data Format

QwAnalaysis

Qweak_R1_Software

Calibration Pulse Experiment and Results

The following are the parameters that were used for the Calibration Pulse experiment.

MCLK = 40Mhz IPreampIn 0xa8 IPreampFeed 0x50 IPreampOut 0x96 IShaper 0x96 IShaperFeed 0x64 IComp 0x78


MSPulseLength<2:0> = 0x0 // MonoStable pulse length of 1 clock period HitCountSel<3:0> = 0x0 // Fast-OR of all 128 channels


The MCLK frequency was chosen because it is at which the original Calibration pulse experiments were run. Also, in the experiment the CalPulse signal supposedly has a peaking time of 22ns. Thus, if we want to have any hope of catching the calibration pulse, we will most likely need to run at at least 40 Mhz. This, of course, also depends on the peak amplitude of the pulse as well as how long its tail is.

The v1495 firmware performs a straight pass-through of the trigger signal from the pattern generator. Care has been taken to make sure that the signals are passed along while they are stable rather than at a transition. Also, it is known that the MCLK shown in Figure 10 of the VFAT manual is out of phase by 180o, thus care has also been taken to make sure that the T1 signal has the proper phase with respect to MCLK. This whole process causes the signal being output to be one clock cycle behind the signal being injected; this shouldn't be a problem.

The "TRIGGER OUT" signal is used as the MCLK for the VFATs and "OUTPUT1" as the T1 signal for the VFAT. OUTPUT1 is set such that it will output the Calpulse signal followed by a single break pulse and then followed by the LV1A signal. The pattern is long enough that we should be able to see whether we received any hits on the lines that we have CalChan turned on in the respective ChanReg. Right now the experiment is running too quickly and does not have the proper setup to see whether the HitCount registers are working properly with the calibration pulses being sent.



[1] Warren_Parsons_Log_Book