Warren Parsons MS Thesis

Warren_Parsons_Log_Book

V1495 User Firmware

GEMReadout.vhd

The main function routines?

GEMReadout_tb.vhd

GEMRxChannel.vhd

GEMRxEventDataFIFO.vhd

a routine controlling the FIFO

GEMRxEventSizeFIFO.vhd

Defines the Event size and structure

GEMTxChannel.vhd

PLLVBlock.vhd

spare_if_rtl.vhd

tristate_if_trl.vhd

v1495usr.vhd

v1495usr_pkg.vhd

v1495usr_hal.vqm

From the v1495 manual this is the v1495 Hardware Abstraction Layer. It is an HDL module provided in Verilog format at the netlist level in order to help interface the hardware.

Reading through this file makes it clear that we are using the Cyclone chip family. I can't find where the "cyclone_lcell" module is defined. I am wondering if it is defined inside of the Quartus II program in a library somewhere. Figuring this out would probably help unravel how our HDL code is actually instantiated in hardware.

General introduction to the readout scheme

CODA Readout

The V1495 module transfers data 16 bits at a time to the ROC. An array within the ROC memory will be filled with the V1495 data stream 16 bits at a time to optimize data throughout. The array within the ROC memory will then be transferred to the host computer and stored.

QwAnalaysis

Qweak_R1_Software

Calibration Pulse Experiment and Results

The following are the parameters that were used for the Calibration Pulse experiment.

MCLK = 40Mhz

This was chosen because it is what the original Calibration pulse experiments were run at. Also, in the experiment the CalPulse signal supposedly has a peaking time of 22ns. Thus, if we want to have any hope of catching that pulse, we will most likely need to run at at least 40 Mhz. This, of course, also depends on the peak amplitude of the pulse as well as how long its tail is.

[1] Warren_Parsons_Log_Book