JLAB PLX LVDS

From New IAC Wiki
Revision as of 03:54, 29 January 2009 by Oborn (talk | contribs)
Jump to navigation Jump to search

A VME Modules designed by Ed Jastrzembski at JLAB

Description:

This PLX board will be built on a Flex I/O format that Ed Jastrzembski developed many years ago. The VME (back end) manages the interface to the bus, and controls two front end 'ports' that can be input or output units.


Media:PLX_BoardLayout.pdf

PLX1.jpgPLX 2.jpg

PLX 3.jpgPLX 4.jpg

PLX 5.jpg

PLX input and output pulses.png


PLX input and output pulses 1.png

Go back VME_modules Go back

Retrieved from "https://wiki.iac.isu.edu/index.php?title=JLAB_PLX_LVDS&oldid=34161"