Difference between revisions of "Warren Parsons MS Thesis"
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[[Qweak_R1_Software]] | [[Qweak_R1_Software]] | ||
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+ | =Calibration Pulse Experiment and Results= | ||
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[http://wiki.iac.isu.edu/index.php/Warren_Parsons_Log_Book] [[Warren_Parsons_Log_Book]] | [http://wiki.iac.isu.edu/index.php/Warren_Parsons_Log_Book] [[Warren_Parsons_Log_Book]] |
Revision as of 15:32, 2 July 2009
VFAT readout card
I2C
Gumstick
V1495 User Firmware
- GEMReadout.vhd
- The main function routines?
- GEMReadout_tb.vhd
- GEMRxChannel.vhd
- GEMRxEventDataFIFO.vhd
- a routine controlling the FIFO
- GEMRxEventSizeFIFO.vhd
- Defines the Event size and structure
- GEMTxChannel.vhd
- PLLVBlock.vhd
- spare_if_rtl.vhd
- tristate_if_trl.vhd
- v1495usr.vhd
- v1495usr_pkg.vhd
- v1495usr_hal.vqm
- From the v1495 manual this is the v1495 Hardware Abstraction Layer. It is an HDL module provided in Verilog format at the netlist level in order to help interface the hardware.
- Reading through this file makes it clear that we are using the Cyclone chip family. I can't find where the "cyclone_lcell" module is defined. I am wondering if it is defined inside of the Quartus II program in a library somewhere. Figuring this out would probably help unravel how our HDL code is actually instantiated in hardware.
General introduction to the readout scheme
Readout Blockdiagram
Changing MCLK frequency
Output MCLK and Level 1 Trigger
VFAT input port
V1495 Data format
CODA Readout
The V1495 module transfers data 16 bits at a time to the ROC. An array within the ROC memory will be filled with the V1495 data stream 16 bits at a time to optimize data throughout. The array within the ROC memory will then be transferred to the host computer and stored.