Difference between revisions of "Warren Parsons Log Book"
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| − | If I understand the underlying functionality of the output of the VFAT2 then the basic idea is that it transfers the hit data from SRAM1 to SRAM2 as soon as there is a LV1A signal (100) sent to the VFAT2 via the "T1" line (after the latency time programmed into the Latency Register with a default setting of 6.4us). Once data is transferred from SRAM1 to SRAM2 it immediately starts outputting the information on " | + | If I understand the underlying functionality of the output of the VFAT2 then the basic idea is that it transfers the hit data from SRAM1 to SRAM2 as soon as there is a LV1A signal (100) sent to the VFAT2 via the "T1" line (after the latency time programmed into the Latency Register with a default setting of 6.4us). Once data is transferred from SRAM1 to SRAM2 it immediately starts outputting the information on "DataOut" at the "MCLK" rate of 40Mhz (I assume to be ultimately governed by the v1495). Valid data can be found on the "DataOut" line as long as the "DataValid" line is high. Thus the LV1A signal on "T1" followed by a transition to high on the "DataValid" line should set off the v1495 data capturing routine. Data is clocked out in FIFO order if more LV1A signals are sent to the VFAT2 before all of the data has been transferred out of the VFAT2. |
=5/19/09= | =5/19/09= | ||
Revision as of 16:08, 18 May 2009
This tracks My Daily Progress developing the VFAT readout
VHDL files for v1495
- GEMReadout.vhd
- The main function routines?
- GEMReadout_tb.vhd
- GEMRxChannel.vhd
- GEMRxEventDataFIFO.vhd
- a routine controlling the FIFO
- GEMRxEventSizeFIFO.vhd
- Defines the Event size and structure
- GEMTxChannel.vhd
- PLLVBlock.vhd
- spare_if_rtl.vhd
- tristate_if_trl.vhd
- v1495usr.vhd
- v1495usr_pkg.vhd
- v1495usr_hal.vhd
5/14/09
Firmware
Today we started looking at the VHDL firmware programs from Ben Raydo at JLab. Our goal: To determine what the general description of the firmware program is and determine an outline of its functionality.
Quartus II
Quartus II has a fairly good tutorial for usage. My goal is to complete this tutorial by the end of the week.
I also started to familiarize myself with the VHDL programming language.
5/15/09
Spent vast majority of day learning VHDL syntax.
Spent some time reviewing the GEM Readout Controller Firmware Status
Spent some time reviewing the v1495 instruction manual ( the Quartus II instructions in particular )
Spent some time reviewing the VFAT instruction manual
- Is there a primer somewhere on how to communicate via/with VME?
- How about this http://www.vita.com/vmefaq.html
I need to write down how to get into the DAQ as well as ROC xterm windows.
- Tamuna can show you the above
5/18/09
- From the manual on the VFAT2: Are we using the Roman Pots or the GEM version for the channel assignments?
If I understand the underlying functionality of the output of the VFAT2 then the basic idea is that it transfers the hit data from SRAM1 to SRAM2 as soon as there is a LV1A signal (100) sent to the VFAT2 via the "T1" line (after the latency time programmed into the Latency Register with a default setting of 6.4us). Once data is transferred from SRAM1 to SRAM2 it immediately starts outputting the information on "DataOut" at the "MCLK" rate of 40Mhz (I assume to be ultimately governed by the v1495). Valid data can be found on the "DataOut" line as long as the "DataValid" line is high. Thus the LV1A signal on "T1" followed by a transition to high on the "DataValid" line should set off the v1495 data capturing routine. Data is clocked out in FIFO order if more LV1A signals are sent to the VFAT2 before all of the data has been transferred out of the VFAT2.