Difference between revisions of "Readout Electronics"
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| − | Inputs to breakout box | + | = I/O= |
| + | ==Inputs to breakout box== | ||
:Trigger (LVDS) | :Trigger (LVDS) | ||
| Line 19: | Line 20: | ||
| − | Timing | + | ==Timing== |
:VFAT: | :VFAT: | ||
| Line 25: | Line 26: | ||
:Progammable through the Latency register (8 bits = 256 bits) you have but only 128 registers data registers. We can go back in time 100 *32 ns = 3 micro seconds. But we only may need 100 ns. | :Progammable through the Latency register (8 bits = 256 bits) you have but only 128 registers data registers. We can go back in time 100 *32 ns = 3 micro seconds. But we only may need 100 ns. | ||
: | : | ||
| − | V1495: can have programmable delay up to? | + | ==V1495: can have programmable delay up to?== |
We can program delays and play with the timing by downloading values for "lat" into the VFAT extended register and set delay on the V1495 through the ROC. | We can program delays and play with the timing by downloading values for "lat" into the VFAT extended register and set delay on the V1495 through the ROC. | ||
| + | |||
| + | |||
| + | The V1495 can also interupt the VME backplane telling a ROC to readout the planes. | ||
| + | |||
| + | =FPGA to VME data transfer= | ||
| + | |||
| + | On 2/15/07 Ben Royd tested the read and write speeds between the VPM backplane and the FPGA user registers. He was able to write 16 bits to USER FPGA in 330 ns. | ||
| + | |||
| + | \RightArrow \frac{16 bits}{330 ns}\times \frac{1 byte}{8 bits} \times \frac{1 ns}{10^9 s} | ||
Revision as of 22:19, 15 January 2008
I/O
Inputs to breakout box
- Trigger (LVDS)
- Clock ( RF synced pulse 31 MHz = 499/16 MHz, LVDS)
- Flip Flop scaner (1 TTL pulse)
V1495 :
- 28 Pin output on 34 pin ribbon cables
- Inputs to V1495:
- 180 bits of data = 12 bits Bunch Counter ( =31 MHz clock) + 12 bit (Event Counter + flags) + 12 bits (Chip ID) + 128 bits (data) + 16 bits (Checksum)
- The input register has been set to a size of 256 bit and there are 12 of them
Timing
- VFAT:
- Progammable through the Latency register (8 bits = 256 bits) you have but only 128 registers data registers. We can go back in time 100 *32 ns = 3 micro seconds. But we only may need 100 ns.
V1495: can have programmable delay up to?
We can program delays and play with the timing by downloading values for "lat" into the VFAT extended register and set delay on the V1495 through the ROC.
The V1495 can also interupt the VME backplane telling a ROC to readout the planes.
FPGA to VME data transfer
On 2/15/07 Ben Royd tested the read and write speeds between the VPM backplane and the FPGA user registers. He was able to write 16 bits to USER FPGA in 330 ns.
\RightArrow \frac{16 bits}{330 ns}\times \frac{1 byte}{8 bits} \times \frac{1 ns}{10^9 s}