Difference between revisions of "VFAT readout electronics"
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| Line 11: | Line 11: | ||
| # || Name || Value || Test rig color <br/> Primary/Second | | # || Name || Value || Test rig color <br/> Primary/Second | ||
|- | |- | ||
| − | | B1 || DGND || Digital Ground | + | | B1 || DGND || Digital Ground || Black/Grey (shared) |
|- | |- | ||
| A1 || DVDD || +2.5V | | A1 || DVDD || +2.5V | ||
| Line 19: | Line 19: | ||
| A2 || SCL || I2C Clock | | A2 || SCL || I2C Clock | ||
|- | |- | ||
| − | | B3 || DGND || Digital Ground | + | | B3 || DGND || Digital Ground || Black/Grey (shared) |
|- | |- | ||
| A3 || DVDD || +2.5V?? | | A3 || DVDD || +2.5V?? | ||
Revision as of 23:44, 13 June 2007
A VFAT board from CERN is evaluated for use as a readout board to convert the GEM output analog signal to a digital signal.
Ribbon cable pinouts
| # | Name | Value | Test rig color Primary/Second |
| B1 | DGND | Digital Ground | Black/Grey (shared) |
| A1 | DVDD | +2.5V | |
| B2 | SDA | I2C Data | |
| A2 | SCL | I2C Clock | |
| B3 | DGND | Digital Ground | Black/Grey (shared) |
| A3 | DVDD | +2.5V?? | |
| B4 | |||
| A4 | |||
| B5 | I2C ADDR | I2C Address (most or least significant??) | |
| A5 | I2C ADDR | I2C Address (most or least significant??) | |
| B6 | I2C ADDR | I2C Address (most or least significant??) | |
| A6 | REH-S | Soft Reset (Program saved) | |
| B7 | |||
| A7 | REH-B | Hard Reset | |
| .............. | |||
|---|---|---|---|
| B22 | DGND | Digital Ground?? | |
| A22 | SCAN E | ||
| B23 | AGND | Analog Ground | |
| A23 | AVDD | 2.5V | |
| B24 | AGND | Analog Ground | |
| A24 | AVDD | 2.5V | |
| B25 | AGNDD | Analog Ground?? | |
| A25 | AVDD | 2.5V | |