Difference between revisions of "CH HPGe Electronics Chain"
Jump to navigation
Jump to search
| Line 1: | Line 1: | ||
| − | HPGe | + | HPGe → Split signal using BNC T junction |
| − | + | → First line to spec amp -> peak sensing ADC | |
| − | + | → Second line to timing/filter amp with ~2.3x amplification (also inverts) | |
| − | + | → Discriminator (Blue lecroy model #xxxx) | |
| − | + | → Top of dual timer then into bottom of dual timer | |
| − | + | → Into 1st gate and delay generator | |
| + | |||
| + | --> positive sent to second gate and delay module | ||
| + | |||
| + | --> negative sent to PADC as gate for spec amp signal | ||
| + | |||
| + | → 2nd gate and delay generator used for ROC signal | ||
Revision as of 17:50, 20 December 2021
HPGe → Split signal using BNC T junction
→ First line to spec amp -> peak sensing ADC
→ Second line to timing/filter amp with ~2.3x amplification (also inverts)
→ Discriminator (Blue lecroy model #xxxx)
→ Top of dual timer then into bottom of dual timer
→ Into 1st gate and delay generator
--> positive sent to second gate and delay module
--> negative sent to PADC as gate for spec amp signal
→ 2nd gate and delay generator used for ROC signal