VFAT powered on and responding to I2C - Revision history

Oborn at 12:25, 8 July 2008

2008-07-08T12:25:30Z

2008-07-08T12:24:22Z

2007-11-06T20:04:52Z

2007-07-24T17:20:07Z

2007-06-27T22:33:06Z

2007-06-27T22:30:21Z

2007-06-27T22:28:47Z

2007-06-27T22:27:35Z

2007-06-27T22:04:04Z

2007-06-27T22:03:29Z

← Older revision		Revision as of 12:25, 8 July 2008
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−
	The image below shows the apparatus used to look at I2C commands		The image below shows the apparatus used to look at I2C commands

−	[[Image:i2c_Apparatus_1.jpg]] <br>	+	[[Image:i2c_Apparatus_1.jpg \| 200 px]] <br>

← Older revision		Revision as of 12:24, 8 July 2008
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		+
		+	The image below shows the apparatus used to look at I2C commands
		+
		+	[[Image:i2c_Apparatus_1.jpg]] <br>
		+
		+
	These are pictures of I2C operations with the VFAT board. In this example the VFAT is set to addresses 0x40 thru 0x4F.		These are pictures of I2C operations with the VFAT board. In this example the VFAT is set to addresses 0x40 thru 0x4F.
		+

	[[Image:i2c_scope_write_42.xfig.png]] <br>		[[Image:i2c_scope_write_42.xfig.png]] <br>

@@ Line 1: / Line 1: @@
 These are pictures of I2C operations with the VFAT board. In this example the VFAT is set to addresses 0x40 thru 0x4F.
-[[Image:i2c_scope_write_42.xfig.png]] <br/>
+[[Image:i2c_scope_write_42.xfig.png]] <br>
 Explanation:
 *START: Master transistions SDA high to low while SCL is high, asserting control of the bus.

@@ Line 5: / Line 5: @@
 *START: Master transistions SDA high to low while SCL is high, asserting control of the bus.
 *ADDRESS: 7-bit address of the slave device, 0x48 or 0b1000010 (IPreampIn) in this case.
-*R/W BIT: Set to 1 for a read operation, 0 for a write operation, 1 (write) in this case
+*R/W BIT: Set to 1 for a read operation, 0 for a write operation, 0 (write) in this case
 *ACK: Slave device pulls down SDA (notice the lower low level from the slave) and the master sends another pulse on SCL to acknowledge the last byte.
 *DATA: 8-bit value, most significant bit first. Slave and master release SCL, allowing it to go high as they transfer or are ready to receive the next bit. In this case the data is 0x18 or 00011000.

← Older revision		Revision as of 22:33, 27 June 2007
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−	These are pictures of ~~i2c~~ operations with the VFAT board. In this example the VFAT is set to addresses 0x40 o 0x4F.	+	These are pictures of I2C operations with the VFAT board. In this example the VFAT is set to addresses 0x40 thru 0x4F.

	[[Image:i2c_scope_write_42.xfig.png]] <br/>		[[Image:i2c_scope_write_42.xfig.png]] <br/>

@@ Line 4: / Line 4: @@
 Explanation:
 *START: Master transistions SDA high to low while SCL is high, asserting control of the bus.
-*ADDRESS: 7-bit address of the slave device, 0x48 or 0b1000010 in this case.
+*ADDRESS: 7-bit address of the slave device, 0x48 or 0b1000010 (IPreampIn) in this case.
 *R/W BIT: Set to 1 for a read operation, 0 for a write operation, 1 (write) in this case
 *ACK: Slave device pulls down SDA (notice the lower low level from the slave) and the master sends another pulse on SCL to acknowledge the last byte.
@@ Line 13: / Line 13: @@
-[[Image:i2c_scope_read_48.png]]<br/>
+[[Image:i2c_scope_read_42.png]]<br/>
-One byte of the VFAT ChipID is read from address 0x48. The value is 0xF3.
+The IPreampIn byte that was just set is read. The address is 0x42 and the value is 0x18.
-[[Image:i2c_scope_write_42.png]]<br/>
+[[Image:i2c_scope_read_48.png]]<br/>
-The IPreampIn byte at address 0x42 has the value 0x18 written to it.
+One byte of the VFAT ChipID is read from address 0x48. The value is 0xF3.

← Older revision		Revision as of 22:27, 27 June 2007
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	[[Image:i2c_scope_write_42.xfig.png]] <br/>		[[Image:i2c_scope_write_42.xfig.png]] <br/>
		+	Explanation:
		+	*START: Master transistions SDA high to low while SCL is high, asserting control of the bus.
		+	*ADDRESS: 7-bit address of the slave device, 0x48 or 0b1000010 in this case.
		+	*R/W BIT: Set to 1 for a read operation, 0 for a write operation, 1 (write) in this case
		+	*ACK: Slave device pulls down SDA (notice the lower low level from the slave) and the master sends another pulse on SCL to acknowledge the last byte.
		+	*DATA: 8-bit value, most significant bit first. Slave and master release SCL, allowing it to go high as they transfer or are ready to receive the next bit.
		+	*ACK: Another ACK to acknowledge the second byte.
		+	*STOP: Master transitions SDA low to high while SCL is high, releasing control of the bus.
		+

← Older revision		Revision as of 22:04, 27 June 2007
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	These are pictures of i2c operations with the VFAT board. In this example the VFAT is set to addresses 0x40 o 0x4F.		These are pictures of i2c operations with the VFAT board. In this example the VFAT is set to addresses 0x40 o 0x4F.
−	[[Image:i2c_scope_write_42.xfig.png]]	+
		+	[[Image:i2c_scope_write_42.xfig.png]] <br/>

← Older revision		Revision as of 22:03, 27 June 2007
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	These are pictures of i2c operations with the VFAT board. In this example the VFAT is set to addresses 0x40 o 0x4F.		These are pictures of i2c operations with the VFAT board. In this example the VFAT is set to addresses 0x40 o 0x4F.
		+	[[Image:i2c_scope_write_42.xfig.png]]
		+

	[[Image:i2c_scope_read_48.png]]<br/>		[[Image:i2c_scope_read_48.png]]<br/>