CAEN V785N ADC - Revision history

Foretony: /* Address */

2021-05-11T22:41:34Z

Address

2016-12-13T22:19:59Z

Data Format

2016-12-13T20:10:21Z

Data Format

2016-12-13T20:06:27Z

Data Format

2016-12-13T19:54:25Z

Documentation & Specs

2016-11-16T23:11:19Z

Standalone functions on 2.6.2

2016-11-15T19:48:04Z

2016-11-15T19:45:12Z

Documentation & Specs

2016-11-15T19:23:45Z

2013-08-05T21:41:52Z

← Older revision		Revision as of 22:19, 13 December 2016
Line 29:		Line 29:

	/data/olddata/r6xxx/r6998.dat		/data/olddata/r6xxx/r6998.dat
		+
		+	<pre>
		+	Found CAEN 785 bank with length 19
		+	Header says 0xfa001000 => 16 converted channels
		+	ADC Ch:0 valid=0 value=83 f8004053
		+	ADC Ch:8 valid=0 value=74 f810404a
		+	ADC Ch:1 valid=0 value=72 f8024048
		+	ADC Ch:9 valid=0 value=78 f812404e
		+	ADC Ch:2 valid=0 value=79 f804404f
		+	ADC Ch:10 valid=0 value=68 f8144044
		+	ADC Ch:3 valid=0 value=283 f806411b
		+	ADC Ch:11 valid=0 value=75 f816404b
		+	ADC Ch:4 valid=0 value=63 f808403f
		+	ADC Ch:12 valid=0 value=65 f8184041
		+	ADC Ch:5 valid=0 value=71 f80a4047
		+	ADC Ch:13 valid=0 value=58 f81a403a
		+	ADC Ch:6 valid=0 value=64 f80c4040
		+	ADC Ch:14 valid=0 value=81 f81c4051
		+	ADC Ch:7 valid=0 value=84 f80e4054
		+	</pre>
		+	{\| border="1" \|cellpadding="20" cellspacing="0
		+	\|colspan= "2" \| Address
		+	\|-
		+	\| Module\|\| address
		+	\|-
		+	\|V775 \|\| 0x610000
		+	\|-
		+	\|V785 \|\| 0x20000
		+	\|-
		+	\|V792 \|\| 0xee0000
		+	\|-
		+	\|V260 \|\| 0xda0000
		+	\|-
		+	\|V1495 \|\| 0x80110000
		+	\|-
		+	\|VX1190 \|\| 0x210000
		+	\|-
		+	\|SIS3610 \|\| 0x3800
		+	\|-
		+	\|JlabF250 \|\| 0
		+	\|-
		+	\|Struck3332\|\| 0x40
		+	\|}

← Older revision		Revision as of 19:54, 13 December 2016
Line 23:		Line 23:

	1 msec Max gate width		1 msec Max gate width
		+
		+	==Data Format==
		+
		+
		+	{\| border="1" \|cellpadding="20" cellspacing="0
		+	\|colspan= "2" \| Address
		+	\|-
		+	\| Module\|\| address
		+	\|-
		+	\|V775 \|\| 0x610000
		+	\|-
		+	\|V785 \|\| 0x20000
		+	\|-
		+	\|V792 \|\| 0xee0000
		+	\|-
		+	\|V260 \|\| 0xda0000
		+	\|-
		+	\|V1495 \|\| 0x80110000
		+	\|-
		+	\|VX1190 \|\| 0x210000
		+	\|-
		+	\|SIS3610 \|\| 0x3800
		+	\|-
		+	\|JlabF250 \|\| 0
		+	\|-
		+	\|Struck3332\|\| 0x40
		+	\|}

	=Address=		=Address=

← Older revision		Revision as of 23:11, 16 November 2016
Line 54:		Line 54:

	A standalone program was created to test the peak sensing ADC functions in the library on the CODA 2.6.2 ROC		A standalone program was created to test the peak sensing ADC functions in the library on the CODA 2.6.2 ROC
		+
		+
		+	error message:
		+	<pre>
		+
		+	initializing the SIS3610
		+	Initialized SIS3610 ID 0 at VME (USER) address 0x3800 (0xacfbb800)
		+	gefVmeAttachCallback failed: code 0x3010000b
		+	ERROR: vmeIntConnect failed
		+	</pre>
		+

@@ Line 24: / Line 24: @@
 msec Max gate width
-=Address==
+=Address=
 const PDC_ADDR = 0x0200000
 =Standalone functions on 2.6.2=

@@ Line 1: / Line 1: @@
 http://www.caentechnologies.com/csite/CaenProd.jsp?parent=11&idmod=285
@@ Line 18: / Line 23: @@
 msec Max gate width
 [[VME_modules]]

← Older revision		Revision as of 21:41, 5 August 2013
Line 2:		Line 2:

	[[File:V785_rev13_Manual.pdf]]		[[File:V785_rev13_Manual.pdf]]
		+
		+	Specs:
		+
		+	0-> +4 Volt input
		+
		+	5.7 us conversion time
		+
		+	12 Bit ADC
		+
		+	50 nsec min rise time for input pulse
		+
		+	1 k-Ohm input impedance
		+
		+	250 nsec min gate width
		+
		+	1 msec Max gate width
		+
		+

	[[VME_modules]]		[[VME_modules]]