A W CAA apparatus - Revision history

Wellali3: /* DAQ readout timing */

2014-10-28T15:37:33Z

DAQ readout timing

Wellali3: /* DAQ readout timing */

2014-10-28T15:36:46Z

DAQ readout timing

Wellali3: /* DAQ readout timing */

2014-10-28T15:33:37Z

DAQ readout timing

Wellali3: /* DAQ readout timing */

2014-10-28T15:33:24Z

DAQ readout timing

Foretony: /* Coincidence timing electronics */

2014-10-27T20:22:20Z

Coincidence timing electronics

Foretony: /* Coincidence timing electronics */

2014-10-27T20:20:00Z

Coincidence timing electronics

Foretony: /* DAQ readout timing */

2014-10-27T20:19:07Z

DAQ readout timing

Foretony: /* DAQ readout timing */

2014-10-27T20:16:41Z

DAQ readout timing

Foretony: /* DAQ readout timing */

2014-10-27T20:10:34Z

DAQ readout timing

Foretony: /* Discrimination */

2014-10-27T20:06:29Z

Discrimination

@@ Line 80: / Line 80: @@
 |}
-The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (<math>t_{stop}</math>) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of t_trig and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
+The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (<math>t_{stop}</math>) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of <math>t_{trig}</math> and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
 ==Coincidence timing electronics==

@@ Line 76: / Line 76: @@
 | [[File:Signal_Diagram_3.png | 600 px]]
 |-
-| Timing Diagram
+| Timing Diagram:<math> t_{stop}=600 ns</math>, <math>t_{trig}= 13 \mu s</math>
 |-
 |}

@@ Line 80: / Line 80: @@
 |}
-The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (<math>t_stop</math>) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of t_trig and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
+The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (<math>t_{stop}</math>) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of t_trig and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
 ==Coincidence timing electronics==

@@ Line 80: / Line 80: @@
 |}
-The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (t_stop) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of t_trig and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
+The output of the coincidence logic unit is used to trigger the data acquisition system.  The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay (<math>t_stop</math>) with an ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. The analog output from the post amplifiers is delayed in time. This delay was of sufficient length that the amplified analog output was in time with the coincidence logic pulse used start a measurement in the PADC.  A copy of that same timed pulse went through a separate gate delay of t_trig and used to signal the DAQ that data was ready to be readout of the VME modules. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals.  A diagram of these signals, their widths, and their timing can be seen in FigureXX.YY.
 ==Coincidence timing electronics==

← Older revision		Revision as of 20:22, 27 October 2014
Line 87:		Line 87:


−	A false coincidence background can be suppressed further by requiring simultaneous signals from both detectors. The 20 ns wide logic pulses produced by the CFD are sent to a time-to-digital converter (TDC) and to a logic unit, after their width has been increase to 100 ns as shown in FigureXX.YY. The logic unit will compare the timing pulses in an AND gate that only provides output if the two pulses are within a 200 nanosecond window. The coincidence output is used to open a linear gate that signals the PADC to look for a peak within a 1 usec window. FigureXX.YY is a plot of the time difference between the two detector pulses thought to be in coincidence. It shows the expected timing window of +/- 100 ns. We ~~can find~~ the probability of having an ~~accidental peak in~~ coincidence by ~~taking~~ the ~~area~~ of ~~the TDC signal and finding the ratio to the~~ accidental background. The probability of an accidental event was approximately 10.19% for a best case scenario and approximately 24.81% for a worst case scenario.	+	A false coincidence background can be suppressed further by requiring simultaneous signals from both detectors. The 20 ns wide logic pulses produced by the CFD are sent to a time-to-digital converter (TDC) and to a logic unit, after their width has been increase to 100 ns as shown in FigureXX.YY. The logic unit will compare the timing pulses in an AND gate that only provides output if the two pulses are within a 200 nanosecond window. The coincidence output is used to open a linear gate that signals the PADC to look for a peak within a 1 usec window. FigureXX.YY is a plot of the time difference between the two detector pulses thought to be in coincidence. It shows the expected timing window of +/- 100 ns. We estimate the probability of having an false coincidence by dividing the number of accidental background event using the number of real coincidence events. The probability of an accidental event was approximately 10.19% for a best case scenario and approximately 24.81% for a worst case scenario.

	==Calibrating Detectors==		==Calibrating Detectors==

← Older revision		Revision as of 20:20, 27 October 2014
Line 87:		Line 87:


−	A false coincidence background can be suppressed further by requiring simultaneous signals from both detectors. The 20 ns wide logic pulses produced by the CFD are sent to a time-to-digital converter (TDC) and to a logic unit, after their width has been increase to 100 ns as shown in FigureXX.YY. The logic unit will compare the timing pulses in an AND gate that only provides output if the two pulses are within a 200 nanosecond window. The coincidence output is used to open a linear gate that signals the PADC to look for a peak within a 1 usec window. FigureXX.YY is a plot of the time difference between the two detector pulses thought to be in coincidence. It shows ~~that~~ the ~~natural range~~ of ~~the signal is~~ +/- 100 ns. We can find the probability of having an accidental peak in coincidence by taking the area of the TDC signal and finding the ratio to the accidental background. The probability of an accidental event was approximately 10.19% for a best case scenario and approximately 24.81% for a worst case scenario.	+	A false coincidence background can be suppressed further by requiring simultaneous signals from both detectors. The 20 ns wide logic pulses produced by the CFD are sent to a time-to-digital converter (TDC) and to a logic unit, after their width has been increase to 100 ns as shown in FigureXX.YY. The logic unit will compare the timing pulses in an AND gate that only provides output if the two pulses are within a 200 nanosecond window. The coincidence output is used to open a linear gate that signals the PADC to look for a peak within a 1 usec window. FigureXX.YY is a plot of the time difference between the two detector pulses thought to be in coincidence. It shows the expected timing window of +/- 100 ns. We can find the probability of having an accidental peak in coincidence by taking the area of the TDC signal and finding the ratio to the accidental background. The probability of an accidental event was approximately 10.19% for a best case scenario and approximately 24.81% for a worst case scenario.

	==Calibrating Detectors==		==Calibrating Detectors==

← Older revision		Revision as of 20:10, 27 October 2014
Line 70:		Line 70:
	==DAQ readout timing==		==DAQ readout timing==

−	~~[[File:Signal_Diagram_3.png \| 600 px]]~~

		+
		+	{\| border="1" \|cellpadding="20" cellspacing="0
		+	\|-
		+	\| [[File:Signal_Diagram_3.png \| 600 px]]
		+	\|-
		+	\| Timing Diagram
		+	\|-
		+	\|}

	The output of the coincidence logic unit is used to trigger the data acquisition system. One output from each of the post amplifier for the analog detector signal introduced a delay in time. Since this delay was of sufficient length, the time taken to form a logic signal was short enough to signal the PADC to measure the peak before it had passed in time. The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay with a ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. A copy of that same timed pulse went through a separate gate delay before triggering the DAQ. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals and then read them out. A diagram of the signals, their widths, and their timing can be seen in FigureXX.YY.		The output of the coincidence logic unit is used to trigger the data acquisition system. One output from each of the post amplifier for the analog detector signal introduced a delay in time. Since this delay was of sufficient length, the time taken to form a logic signal was short enough to signal the PADC to measure the peak before it had passed in time. The trigger was sent into a CAEN Dual Timer with multiple outputs. One output was given a fixed delay with a ORTEC Gate Delay Generator before going to the common stop of the TDC. A second timed pulse, one microsecond wide, was sent to the PADC gate. A copy of that same timed pulse went through a separate gate delay before triggering the DAQ. The trigger was delayed to allow time for the DAQ to convert the analog signals to digital signals and then read them out. A diagram of the signals, their widths, and their timing can be seen in FigureXX.YY.

@@ Line 63: / Line 63: @@
 ==Discrimination==
-For our experiment we used two Canberra 2035A Constant Fraction Timing SCA which performed  both energy and timing analysis on post amplified analog pulses. The amplitude of the analog signal is typically proportional to the energy a photon deposits in the detector. Low energy background events are reduced using the discriminator. Both CFD modules where set to accept 60 keV photons or greater. The output logic pulse from this constant fraction discriminator occurs at the same point in the rise of input pulse. To accomplish this, the analog pulse into the discriminator is superimposed onto a copy of that input that has been inverted, attenuated,  and offset in time.  Adding the two signals yields a bipolar signal. A timing discriminator triggers on the zero-crossing of the signal, producing an output logic pulse. After the CFD, one pulse, with a pulse width of 20 ns, went straight to the a time-to-digital converter (TDC). A copy of that same pulse went to two gate generators that where used to increase the pulse widths to 100 ns. This increase in the width of the logic pulse corresponds to a 200 ns timing window for coincidence events.   In other words, a coincidence is thought to exist if the two output signals occur within 200 seconds of each other.
+For our experiment we used two Canberra 2035A Constant Fraction Timing SCA which performed  both energy and timing analysis on post amplified analog pulses. The amplitude of the analog signal is typically proportional to the energy a photon deposits in the detector. Low energy background events are reduced using the discriminator. Both CFD modules where set to accept 60 keV photons or greater. The output logic pulse from this constant fraction discriminator occurs at the same point in the rise of input pulse. To accomplish this, the analog pulse into the discriminator is superimposed onto a copy of that input that has been inverted, attenuated,  and offset in time.  Adding the two signals yields a bipolar signal. A timing discriminator triggers on the zero-crossing of the signal, producing an output logic pulse. After the CFD, one pulse, with a pulse width of 20 ns, went straight to the a time-to-digital converter (TDC start). A copy of that same pulse went to two gate generators that where used to increase the pulse widths to 100 ns. This increase in the width of the logic pulse corresponds to a 200 ns timing window for coincidence events.   In other words, a coincidence is thought to exist if the two output signals occur within 200 seconds of each other.
 [[File:Canberra2037A.pdf]]
 ==DAQ readout timing==